LP5526

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SNVS431D – FEBRUARY 2006 – REVISED MARCH 2013

Table 9. GPIO DATA (07H)

Name

Bit

Description

DATA[2:0]

2:0

Data bits

GPIO control register is used to set the direction of each GPIO pin. For example, by setting OEN0 bit high the

GPIO[0]/PWM pin acts as a logic output pin with data defined DATA0 in GPIO data register. Note, that the

EN_PWM_PIN bit overrides OEN0 state by forcing GPIO[0]/PWM to act as PWM input. GPIO[1] and GPIO[2]

pins can be selected to be inputs or outputs, defined by OEN1 and OEN2 bit status. PWM functionality is valid

only for GPIO[0]/PWM pin. GPIO data register contains the data of GPIO pins. When output direction is selected

to GPIO pin, then GPIO data register defines the output pin state. When GPIO data register is read, it contains

the state of the pin despite of the pin direction.

Parameter

Test Conditions

Min

Typ

Max

Unit

LOGIC INPUT SCL, SDA, GPIO[0:2]

Input low level

V

Input high level

0.8 ×

V

Logic input current

−1.0

1.0

µA

Clock frequency

400

kHz

LOGIC INPUT NRST

Input low level

0.5

V

Input high level

1.2

V

Input current

-1.0

1.0

µA

Reset pulse width

10

µs

LOGIC OUTPUT SDA

Output low level

0.3

0.5

V

Output high level

0.5

0.3

Output leakage current

1.0

µA

LOGIC OUTPUT GPIO[0:2]

Output low level

0.3

0.5

V

Output high level

V

0.5

0.3

Output leakage current

1.0

µA

I

The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of

the data line can only be changed when CLK is LOW.

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