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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST7FLCD1 датащи(PDF) 48 Page - STMicroelectronics |
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ST7FLCD1 датащи(HTML) 48 Page - STMicroelectronics |
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48 / 95 page  PWM Generator ST7FLCD1 48/95 This register adjusts the PWM frequency (setting the PWM duty cycle resolution) for outputs PWM[3:0]. CONTROL REGISTER B (PWMCRB) Read/Write Reset Value: 0000 0000 (00h) Bits [7:6] = Reserved. Forced by hardware to 0. Bits [5:4] = OE[5:4] PWM Output Enable. These bits are set and cleared by software. They enable or disable the PWM output channels independently acting on the corresponding I/O pin. 0 the PWM pin is a general I/O. 1 the PWM pin is driven by the PWM peripheral. Bits [3:2] = Reserved. Forced by hardware to 0. Bit [1:0] = OP[5:4] PWM Output Polarity. These bits are set and cleared by software. They independently select the polarity of the 4 PWM output signals. 0 positive polarity. 1 negative polarity. Note: When an OPx bit is modified, the PWMx output signal is immediately reversed. AUTO-RELOAD REGISTER B (PWMARRB) Read/Write Reset Value: 1111 1111 (FFh) Bits [7:0] = AR [7:0] Counter Auto-Reload Data. These bits are set and cleared by software. They are used to hold the auto-reload value which is automatically loaded in the counter when an overflow occurs. Writing in this register reload the PWM counter to ARR B value. At the same time, the PWM output levels are changed according to the corresponding OPx bit in the PWMCR register. This register adjusts the PWM frequency (by setting the PWM duty cycle resolution) for outputs PWM[5:4]. 76 54 321 0 0 0 OE5 OE4 0 0 OP5 OP4 76 54 321 0 AR73 AR6 AR5 AR4 AR3 AR2 AR1 AR0 |
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