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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST7FLCD1 датащи(PDF) 92 Page - STMicroelectronics |
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ST7FLCD1 датащи(HTML) 92 Page - STMicroelectronics |
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92 / 95 page  Electrical Characteristics ST7FLCD1 92/95 17.8 I2C/DDC Bus Timings Note:1. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. 2. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of SCL signal. 3. Cb = total capacitance of one bus line in pF. 4. I²C parameters compliant with I²C Bus Specification for speeds up to 400 kHz only. Faster speeds are at user responsibility. Symbol Parameter Standard I2C Fast I2C Unit Min. Max. Min. Max. tBUF Bus free time between a STOP and START condition 4.7 1.3 ms tHD:STA Hold time START condition. After this period, the first clock pulse is generated 4.0 0.6 ms tLOW LOW period of the SCL clock 4.7 1.3 ms tHIGH HIGH period of the SCL clock 4.0 0.6 ms tSU:STA Set-up time for a repeated START condition 4.7 0.6 ms tHD:DAT Data hold time 0 (1) 0 (1) 0.9(2) ns tSU:DAT Data set-up time 250 100 ns tR Rise time of both SDA and SCL signals 1000 20+0.1Cb 300 ns tF Fall time of both SDA and SCL signals 300 20+0.1Cb 300 ns tSU:STO Set-up time for STOP condition 4.0 0.6 ns Cb Capacitive load for each bus line 400 400 pF Figure 44: I²C Bus Timing tBUF tLOW tHIGH tHD,STA tR tF tSU,STA tHD,DAT tSU,DAT tSU,STO SDA SCL SDA |
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