THS6092SLASH3 datasheet(22/46 Pages) TI1

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THS6042, THS6043

350 mA, ±12 V ADSL CPE LINE DRIVERS

SLOS264G − MARCH 2000 − REVISED DECEMBER 2001

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

APPLICATION INFORMATION

PCB design considerations

Proper PCB design techniques in two areas are important to assure proper operation of the THS6042/3. These

areas are high-speed layout techniques and thermal-management techniques. Because the devices are

high-speed parts, the following guidelines are recommended.

D Ground plane − It is essential that a ground plane be used on the board to provide all components with a

low inductive ground connection. Although a ground connection directly to a terminal of the THS6042/3 is

not necessarily required, it is highly recommended that the thermal pad of the package be tied to ground.

This serves two functions. It provides a low inductive ground to the device substrate to minimize internal

crosstalk and it provides the path for heat removal.

D Input stray capacitance − To minimize potential problems with amplifier oscillation, the capacitance at the

inverting input of the amplifiers must be kept to a minimum. To do this, PCB trace runs to the inverting input

must be as short as possible, the ground plane must be removed under any etch runs connected to the

inverting input, and external components should be placed as close as possible to the inverting input. This

is especially true in the noninverting configuration. An example of this can be seen in Figure 41, which shows

what happens when a 2.2-pF capacitor is added to the inverting input terminal in the noninverting

configuration. The bandwidth increases dramatically at the expense of peaking. This is because some of

the error current is flowing through the stray capacitor instead of the inverting node of the amplifier. While

the device is in the inverting mode, stray capacitance at the inverting input has a minimal effect. This is

because the inverting node is at a virtual ground and the voltage does not fluctuate nearly as much as in

the noninverting configuration. This can be seen in Figure 42, where a 22-pF capacitor adds only 0.9 dB

of peaking. In general, as the gain of the system increases, the output peaking due to this capacitor

decreases. While this can initally appear to be a faster and better system, overshoot and ringing are more

likely to occur under fast transient conditions. So, proper analysis of adding a capacitor to the inverting input

node should always be performed for stable operation.

Figure 41

−10

−8

−6

−4

−2

750

Ω

C in

−

Ω

100 k

OUTPUT AMPLITUDE

FREQUENCY

1 G

f − Frequency − Hz

1 M

10 M

100 M

VCC = ±12 V

Gain = 1

RL = 50 Ω

VO = 0.1 V

Ci = 0 pF

(Stray C Only)

Ci = 2.2 pF

Figure 42

−7

−6

−5

−4

−3

−2

−1

100 k

OUTPUT AMPLITUDE

FREQUENCY

1 G

f − Frequency − Hz

1 M

10 M

100 M

750

Ω

C in

−

RL = 50 Ω

Ω

Ci = 0 pF

(Stray C Only)

Ci = 22 pF

VCC = ±12 V

Gain = −1

RL = 50 Ω

VO = 0.1 V

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