CONTROL

1/4 CD4049

47 k:

50:

47 k:

50:

1.3 k:

1.3 k:

1.3 k:

1.3 k:

+

-

5

6

3

4

3

2

2

8

6

8

3

2

U1

U2

1/4 CD4049

LMH6732

+

-

LMH6732

1

8

+5V

FOR LMH6732

PIN NUMBERS SHOWN

FOR SOIC PACKAGE

TO PIN 8 OF

LMH6732

OPEN COLLECTOR

TTL GATE

LMH6732

www.ti.com

SNOSA47B – FEBRUARY 2003 – REVISED MARCH 2013

Figure 63. Controlling Power On State with TTL Logic (Open Collector Output)

"POPLESS OUTPUT" & OFF CONDITION OUTPUT STATE

The LMH6732 has been especially designed to have minimum glitches during turn-on and turn-off. This is

advantageous in situations where the LMH6732 output is fed to another stage which could experience false auto-

ranging, or even worse reset operation, due to these transient glitches. Example of this application would be an

AGC circuit or an ADC with multiple ranges set to accommodate the largest input amplitude. For the LMH6732,

these sorts of transients are typically less than 50mV in amplitude (see Electrical Characteristics Tables for

Typical values). Applications designed to utilize the CLC505's low output glitch would benefit from using the

LMH6732 instead since the LMH6732's output glitch is improved to be even lower than the CLC505's. In the "Off

State", the output stage is turned off and is in effect put into a high-Z state. In this sate, output can be forced by

other active devices. No significant current will flow through the device output pin in this mode of operation.

MUX APPLICATION

Since The LMH6732's output is essentially open in the “off” state, it is a good candidate for a fast 2:1 MUX.

Figure 64 shows one such application along with the output waveform in Figure 65 displaying the switching

between a continuous triangle wave and a single cycle sine wave (signals trigger locked to each other for stable

scope photo). Switching speed of the MUX will be less than 50 ns and is governed by the “Ton" and “Toff” times

Figure 64. 50 ns 2:1 MUX Schematic

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