LMH6732MFXSLASHNOPB datasheet(18/29 Pages) TI1

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| 5pF*

PIN NUMBERS SHOWN

FOR SOIC PACKAGE

TO PIN 8 OF

LMH6732

CMOS LOGIC GATE

(WITH ±5V OUTPUT SWING)

* EXPERIMENTALLY

ADJUSTED VALUE

LMH6732

SNOSA47B – FEBRUARY 2003 – REVISED MARCH 2013

www.ti.com

The relationship between ICC and IP is given by:

lP = ICC/57 (approximate ratio at ICC = 3.4mA; consult Figure 45 for relationship at any ICC).

Knowing IP leads to a direct calculation of RP.

RP + 5kΩ = [(V

+ -1.6)-V−]/ I

RP+ 5kΩ= =8.4 /IP (for V

+ = 5V and V− = −5V).

First, an operating point needs to be determined from the plots & specifications as discussed above. From this, IP

is obtained. Knowing IP and the potential RP is tied to, RP can be calculated.

EXAMPLE

An application requires that VS = ±3V and performance in the 1mA operating point range. The required IP can

therefore be determined as follows:

IP=21μA

RP is connected from pin 8 to V

−. Calculate R

P under these conditions:

RP+ 5kΩ = [(V

+ -1.6)-V−] / I

RP+ 5kΩ = [(3V-1.6V) - (-3V)] / 21μA

RP = 205kΩ

The LMH6732 will have performance similar to RP = 412kΩ shown on the datasheet, but with 40% less power

dissipation due to the reduced supply voltages. The op amp will also have a more restricted common-mode

range and output swing.

DYNAMIC SHUTDOWN CAPABILITY

The LMH6732 may be powered on and off very quickly by controlling the voltage applied to RP. If RP is

connected between pin 8 and the output of a CMOS gate powered from ±5V supplies, the gate can be used to

turn the amplifier on and off. This is shown in Figure 62 below:

Figure 62. Dynamic Control of Power Consumption Using CMOS Logic

When the gate output is switched from high to low, the LMH6732 will turn on. In the off state, the supply current

typically reduces to 1

μA or less. The LMH6732's "off state" supply current is reduced significantly compared to

the CLC505. This extremely low supply current in the "off state" is quite advantageous since it allows for

significant power saving and minimizes feed-through. To improve switching time, a speed up capacitor from the

gate output to pin 8 is recommended. The value of this capacitor will depend on the RP value used and is best

established experimentally. Turn-on and turn-off times of <20ns (ICC = 9mA) are achievable with ordinary CMOS

gates.

EXAMPLE

An open collector logic device is used to dynamically control the power dissipation of the circuit. Here, the

desired connection for RP is from pin 8 to the open collector logic device.

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