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FPD87392 датащи(PDF) 14 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
номер детали FPD87392
подробное описание детали  3.3V TFT-LCD Timing Controller with Dual LVDS Inputs/Dual RSDS??Outputs for TFT-LCD Monitor and Notebook (SXGA/SXGA/UXGA)
PDF  30 Pages
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производитель  NSC [National Semiconductor (TI)]
домашняя страница  http://www.national.com
Logo NSC - National Semiconductor (TI)

FPD87392 датащи(HTML) 14 Page - National Semiconductor (TI)

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Output Timing—TTL
Parameter
Comments
(TPW, OE2, OE1 : 3’b000)
SXGA
@ 54 MHz
SXGA+
@ 54 MHz
UXGA
@ 81 MHz
Remarks/
Unit
t1
STH Rising to Active Data
2
2
2
CLKP/N
t2
High Duration of STH
1
1
1
CLKP/N
t3
STH Rising to TP Rising
660
720
820
CLKP/N
t4
High Duration of TP
54
54
81
CLKP/N
t5
STH Rising to OE Falling
687
747
861
CLKP/N
t6
High Duration of OE
189
189
284
CLKP/N
t7
STH Rising to CPV
660
720
820
CLKP/N
t8
High Duration of CPV
422
422
540
CLKP/N
t9
STH Rising to STV
238
298
280
CLKP/N
t10
High Duration of STV
1
(844)
1
(844)
1
(1080)
Line
(CLKP/N)
t11
STH Rising to REV (1 LINE)
645
705
805
CLKP/N
t12
High/Low Duration of REV (1 LINE)
1
(844)
1
(844)
1
(1080)
Line
(CLKP/N)
t13
STH Rising to REV2 (1 + 2 LINE)
645
705
805
CLKP/N
t14
High/Low Duration of REV2 (1 + 2 LINE)
1 (the first line)/2
(844/1688)
1 (the first line)/2
(844/1688)
1 (the first line)/2
(1080/2160)
Line
(CLKP/N)
Line = Hsync Cycle
TP/OE Duty Control Configuration
Resolution
TPW
OEW2
OEW1
TP
OE
(µs)
@ 54 MHz
(CLK)
@ 81 MHz
(CLK)
SXGA, SXGA+
@ 54 MHz
UXGA
@ 81 MHz
00
0
1.0 µs
54 CLK @ 54 MHz
27 CLK @ 81 MHz
3.5
189
284
0
0
1
3.0
162
243
0
1
0
2.5
135
203
0
1
1
2.0
108
162
10
0
0.5 µs
27 CLK @ 54 MHz
41 CLK @ 81 MHz
3.5
189
284
1
0
1
3.0
162
243
1
1
0
2.5
135
203
1
1
1
2.0
108
162
www.national.com
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