4.7uF

10uF

3.3uH

LM3205

SNVS388E – JULY 2005 – REVISED APRIL 2013

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Figure 34. Evaluation Board for WSON

BOARD LAYOUT FLOW (WSON)

important.

2. Minimize L1, C2, SW and PGND loop. These traces also should be wide and short. This is the second

priority.

3. Above layout patterns should be placed on the component side of the PCB to minimize parasitic inductance

and resistance due to via-holes. It may be a good idea that the SW to L1 path is routed between C2(+) and

C2(-) land patterns. If vias are used in these large current paths, multiple via-holes should be used if

possible.

4. Connect C1(-), C2(-) and PGND with wide GND pattern. This pattern should be short, so C1(-), C2(-), and

PGND should be as close as possible. Then connect to a PCB common GND pattern with as many via-holes

as possible.

5. SGND should connect directly to PGND through a single common via as close to C1 as possible. Connecting

these pins under the WSON device on a different layer should be avoided.

7. FB line should be protected from noise. It is a good idea to use an inner GND layer (if available) as a shield.

NOTE

The evaluation board shown in Figure 33 and Figure 34 for the LM3205TL/LM3205SD

were designed with these considerations, and it shows good performance. However some

aspects have not been optimized because of limitations due to evaluation-specific

requirements. The board can be used as a reference, but it is not the best. Please refer

questions to a TI representative.

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