FB

EN

SW

2.7V to 5.5V

10 PF

4.7 PF

SGND

PGND

3.3 PH

C1

C2

L1

E

C

i

i

Fosc = 2 MHz

+

+

-

-

LM3205

SNVS388E – JULY 2005 – REVISED APRIL 2013

www.ti.com

BOARD LAYOUT CONSIDERATIONS

Figure 32. Current Loop

The LM3205 converts higher input voltage to lower output voltage with high efficiency. This is achieved with an

inductor-based switching topology. During the first half of the switching cycle, the internal PMOS switch turns on,

through the inductor. During the second half cycle, the PMOS turns off and the internal NMOS turns on. The

inductor current continues to flow via the inductor from the device PGND line to the output capacitor (C2).

Referring to Figure 32 , the LM3205 has two major current loops where pulse and ripple current flow. The loop

shown in the left hand side is most important, because pulse current shown in Figure 32 flows in this path. The

right hand side is next. The current waveform in this path is triangular, as shown in Figure 32 . Pulse current has

many high-frequency components due to fast di/dt. Triangular ripple current also has wide high-frequency

components. Board layout and circuit pattern design of these two loops are the key factors for reducing noise

radiation and stable operation. Other lines, such as from battery to C1(+) and C2(+) to load, are almost DC

current, so it is not necessary to take so much care. Only pattern width (current capability) and DCR drop

considerations are needed.

16

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