LM3205TLXSLASHNOPB datasheet(17/28 Pages) TI1

17 / 28 page

3.3 ÛH

10 ÛF

4.7 ÛF

LM3205

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SNVS388E – JULY 2005 – REVISED APRIL 2013

Figure 33. Evaluation Board Layout for DSBGA

BOARD LAYOUT FLOW (DSBGA)

1. Minimize C1, PVIN, and PGND loop. These traces should be as wide and short as possible. This is most

important.

2. Minimize L1, C2, SW and PGND loop. These traces also should be wide and short. This is the second

priority.

3. Above layout patterns should be placed on the component side of the PCB to minimize parasitic inductance

and resistance due to via-holes. It may be a good idea that the SW to L1 path is routed between C2(+) and

C2(-) land patterns. If vias are used in these large current paths, multiple via-holes should be used if

possible.

4. Connect C1(-), C2(-) and PGND with wide GND pattern. This pattern should be short, so C1(-), C2(-), and

PGND should be as close as possible. Then connect to a PCB common GND pattern with as many via-holes

as possible.

5. SGND should not connect directly to PGND. Connecting these pins under the device should be avoided. (If

possible, connect SGND to the common port of C1(-), C2(-) and PGND.)

6. VDD should not be connected directly to PVIN. Connecting these pins under the device should be avoided. It

is good idea to connect VDD to the C1(+) to avoid switching noise injection to the VDD line.

7. FB line should be protected from noise. It is a good idea to use an inner GND layer (if available) as a shield.

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