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WM8998 датащи(PDF) 28 Page - Wolfson Microelectronics plc

номер детали WM8998
подробное описание детали  High Performance Audio Hub CODEC
PDF  307 Pages
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производитель  WOLFSON [Wolfson Microelectronics plc]
домашняя страница  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8998 датащи(HTML) 28 Page - Wolfson Microelectronics plc

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WM8998
Production Data
w
PD, October 2014, Rev 4.0
28
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK & FREQUENCY LOCKED LOOP (FLL)
MCLK
tMCLKL
tMCLKH
tMCLKY
VIH
VIL
Figure 1 Master Clock Timing
Test Conditions
The following timing information is valid across the full range of recommended operating conditions.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Master Clock Timing (MCLK1, MCLK2)
MCLK frequency
MCLK as input to FLL,
FLLn_REFCLK_DIV=00
13.5
MHz
MCLK as input to FLL,
FLLn_REFCLK_DIV=01
27
MCLK as input to FLL,
FLLn_REFCLK_DIV=10 or 11
40
MCLK as direct SYSCLK or
ASYNCCLK source
25
MCLK duty cycle
MCLK as input to FLL
80:20
20:80
%
MCLK as direct SYSCLK or
ASYNCCLK source
60:40
40:60
MCLK2 frequency
Sleep Mode
32.768
kHz
Frequency Locked Loops (FLL1, FLL2)
FLL input frequency
FLLn_REFCLK_DIV=00
0.032
13.5
MHz
FLLn_REFCLK_DIV=01
0.064
27
FLLn_REFCLK_DIV=10
0.128
40
FLLn_REFCLK_DIV=11
0.256
40
FLL synchroniser input
frequency
FLLn_SYNCCLK_DIV=00
0.032
13.5
MHz
FLLn_SYNCCLK_DIV=01
0.064
27
FLLn_SYNCCLK_DIV=10
0.128
40
FLLn_SYNCCLK_DIV=11
0.256
40



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