WM5102 datasheet(49/334 Pages) WOLFSON

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WM5102

PD, June 2014, Rev 4.2

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

IN2R_ENA_STS

Input Path 2 (Right) Enable Status

0 = Disabled

1 = Enabled

IN1L_ENA_STS

Input Path 1 (Left) Enable Status

0 = Disabled

1 = Enabled

IN1R_ENA_STS

Input Path 1 (Right) Enable Status

0 = Disabled

1 = Enabled

Table 2 Input Signal Path Enable

INPUT SIGNAL PATH SAMPLE RATE CONTROL

The input signal paths may be selected as input to the digital mixers or signal processing functions

within the WM5102 digital core. The sample rate for the input signal paths is configured using the

IN_RATE register - see Table 21 within the “Digital Core” section.

Note that sample rate conversion is required when routing the input signal paths to any signal chain

that is asynchronous and/or configured for a different sample rate.

INPUT SIGNAL PATH CONFIGURATION

The WM5102 supports six input signal paths. Each pair of inputs can be configured as single-ended,

differential, or digital microphone configuration. Note that the mode is configurable for each stereo pair

of inputs; the Left and Right channels of any pair of inputs are always in the same mode.

The input signal path configuration is selected using the INn_MODE registers (where ‘n’ identifies the

associated input). The external circuit configurations are illustrated on the previous pages.

The analogue input signal paths (single-ended or differential) each incorporate a PGA to provide gain

in the range 0dB to +31dB in 1dB steps. Note that these PGAs do not provide pop suppression

functions; it is recommended that the gain should not be adjusted whilst the respective signal path is

enabled.

The analogue input PGA gain is controlled using the INnL_PGA_VOL and INnR_PGA_VOL registers.

Note that separate volume control is provided for the Left and Right channels of each stereo pair.

When the input signal path is configured for digital microphone input, the voltage reference for the

associated input/output pins is selectable using the INn_DMIC_SUP registers - each interface may be

referenced to MICVDD, or to the MICBIAS1, MICBIAS2 or MICBIAS3 levels.

A digital delay may be applied to any of the digital microphone input channels. This feature can be

used for phase adjustment of any digital input, including directional control of multiple microphones.

The delay is controlled using the INnL_DMIC_DLY and INnR_DMIC_DLY registers.

The MICVDD voltage is generated by an internal Charge Pump and LDO Regulator. The MICBIAS1,

MICBIAS2 and MICBIAS3 outputs are derived from MICVDD - see “Charge Pumps, Regulators and

Voltage Reference”.

Under default register conditions, the input signal paths are configured for highest performance. This

can be adjusted using the INn_OSR registers, which provide control of the DMICCLKn frequency and

the ADC oversample rate.

The input signal paths are configured using the register bits described in Table 3.

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