48

DIN[19]

47

DIN[18]

46

DIN[17]

45

DIN[16]

44

DIN[15]

43

42

41

DIN[14]

40

DIN[13]

39

DIN[12]

38

DIN[11]

37

DIN[10]

13

14

15

16

17

18

19

20

21

22

23

24

RESRVD

DEN

DOUT-

DOUT+

NC

DS99R101

48 PIN TQFP

DS99R101, DS99R102

www.ti.com

SNLS240D – MARCH 2007 – REVISED APRIL 2013

DS99R101 Pin Diagram

Figure 17. Serializer - DS99R101

TOP VIEW

DS99R102 Deserializer Pin Descriptions

Pin #

Pin Name

I/O

Description

LVCMOS PARALLEL INTERFACE PINS

25-28, ROUT[7:0]

LVCMOS_O

Receiver Parallel Interface Data Outputs – Group 1

31-34

13-16, ROUT[15:8]

LVCMOS_O

Receiver Parallel Interface Data Outputs – Group 2

21-24

3-6, 9- ROUT[23:16]

LVCMOS_O

Receiver Parallel Interface Data Outputs – Group 3

12

18

RCLK

LVCMOS_O

Parallel Interface Clock Output Pin. Strobe edge set by RRFB configuration pin.

CONTROL AND CONFIGURATION PINS

43

RRFB

LVCMOS_I

Receiver Clock Edge Select Pin

RRFB = H; ROUT LVCMOS Outputs strobed on the Rising Clock Edge.

RRFB = L; ROUT LVCMOS Outputs strobed on the Falling Clock Edge.

48

REN

LVCMOS_I

Receiver Data Enable

REN = H; ROUT[23-0] and RCLK are Enabled (ON).

REN = L; ROUT[23-0] and RCLK are Disabled (OFF), Receiver ROUT[23-0] and RCLK Outputs

are in TRI-STATE, PLL still operational and locked to TCLK.

1

RPWDNB

LVCMOS_I

Receiver Data Enable

REN = H; ROUT[23-0] and RCLK are Enabled (ON).

REN = L; ROUT[23-0] and RCLK are Disabled (OFF), Receiver ROUT[23-0] and RCLK Outputs

are in TRI-STATE, PLL still operational and locked to TCLK.

17

LOCK

LVCMOS_O

LOCK indicates the status of the receiver PLL

LOCK = H; receiver PLL is locked

LOCK = L; receiver PLL is unlocked, ROUT[23-0] and RCLK are TRI-STATED

2

RESRVD

LVCMOS_I

RESERVED – This pin MUST be tied LOW.

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