DS99R101, DS99R102

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SNLS240D – MARCH 2007 – REVISED APRIL 2013

Serializer Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

LVDS Low-to-High Transition Time

0.6

ns

LVDS High-to-Low Transition Time

0.6

ns

VODSEL = L

DIN (23:0) Setup to TCLK

5

ns

(1)

DIN (23:0) Hold from TCLK

5

ns

DOUT ± HIGH to TRI-STATE Delay

15

ns

DOUT ± LOW to TRI-STATE Delay

15

ns

DOUT ± TRI-STATE to HIGH Delay

200

ns

DOUT ± TRI-STATE to LOW Delay

200

ns

Serializer PLL Lock Time

10

ms

Serializer Delay

(3)

3.5T

3.5T + 2.85

ns

VODSEL = L, TRFB = H

+ 10

(3)

3.5T

3.5T + 2.85

ns

VODSEL = L, TRFB = L

+ 10

TxOUT_E_O

TxOUT_Eye_Opening

3–40 MHz

0.68

(respect to ideal)

(1)

Specification is guaranteed by characterization and is not tested in production.

(2)

When the Serializer output is at TRI-STATE, the Deserializer will lose PLL lock. Resynchronization MUST occur before data transfer.

(3)

Figure 1, Figure 2, Figure 8, Figure 12, Figure 14 show a falling edge data strobe (TCLK IN/RCLK OUT).

(4)

(5)

UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency.

Deserializer Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol

Parameter

Conditions

Pin/Freq.

Min

Typ

Max

Units

Receiver out Clock Period

(1)

RCLK

25

T

333

ns

RCLK Duty Cycle

RCLK

45

50

55

%

LVCMOS Low-to-High

ROUT [23:0],

2.5

3.5

ns

Transition Time

(lumped load)

LOCK, RCLK

(Figure 11)

LVCMOS High-to-Low

2.5

3.5

ns

Transition Time

ROUT (7:0) Setup Data to

(Figure 15)(2)

ROUT [7:0]

(0.40)*

ns

RCLK (Group 1)

ROUT (7:0) Hold Data to RCLK

(0.40)*

ns

(Group 1)

ROUT (15:8) Setup Data to

(Figure 15)(2)

ROUT [15:8],

(0.40)*

ns

RCLK (Group 2)

LOCK

ROUT (15:8) Hold Data to

(0.40)*

ns

RCLK (Group 2)

ROUT (23:16) Setup Data to

(Figure 15)(2)

ROUT [23:16]

(0.40)*

ns

RCLK (Group 3)

ROUT (23:16) Hold Data to

(0.40)*

ns

RCLK (Group 3)

HIGH to TRI-STATE Delay

(Figure 13)

ROUT [23:0],

3

10

ns

RCLK, LOCK

LOW to TRI-STATE Delay

3

10

ns

TRI-STATE to HIGH Delay

3

10

ns

TRI-STATE to LOW Delay

3

10

ns

Deserializer Delay

(Figure 12)(3)

RCLK

[4+(3/56)]T

[4+(3/56)]T

ns

+5.9

+18.5

(1)

Specification is guaranteed by characterization and is not tested in production.

(2)

Figure 5, Figure 15 show a rising edge data strobe (TCLK IN/RCLK OUT).

(3)

Figure 1, Figure 2, Figure 8, Figure 12, Figure 14 show a falling edge data strobe (TCLK IN/RCLK OUT).

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