80%

20%

80%

20%

Vdiff = 0V

Differential

Signal

Vdiff = (DOUT+) - (DOUT-)

100:

DOUT+

DOUT-

10 pF

10 pF

RCLK

ODD ROUT

EVEN ROUT

Signal Pattern

Device Pin Name

TCLK

ODD DIN

EVEN DIN

Signal Pattern

Device Pin Name

DS99R101, DS99R102

SNLS240D – MARCH 2007 – REVISED APRIL 2013

www.ti.com

Deserializer Switching Characteristics (continued)

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol

Parameter

Conditions

Pin/Freq.

Min

Typ

Max

Units

Deserializer PLL Lock Time

(Figure 14) (3)

3 MHz

5

50

ms

(5) (1)

40 MHz

5

50

ms

RxIN_TOL_L

Receiver INput TOLerance

(Figure 16)

3 MHz–40 MHz

0.25

UI

Left

(6) (1) (7)

RxIN_TOL_R Receiver INput TOLerance

(Figure 16)

3 MHz–40 MHz

0.25

UI

Right

(6) (1) (7)

(4)

synchronization pattern.

(5)

(6)

RxIN_TOL is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors

occur. It is a measurement in reference with the ideal bit position, please see AN-1217 (SNLA053) for detail.

(7)

UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency.

AC Timing Diagrams and Test Circuits

Figure 1. Serializer Input Checker-board Pattern

Figure 2. Deserializer Output Checker-board Pattern

Figure 3. Serializer LVDS Output Load and Transition Times

6

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