REV. A

ADP3421

–4–

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the ADP3421 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

*

Input Supply Voltage (VCC) . . . . . . . . . . . . . . –0.3 V to +7 V

UVLO Input Voltage . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

All Other Inputs/Outputs . . . . . . . . . . . . . . . . . . VCC + 0.3 V

Operating Ambient Temperature Range . . . . . . 0

°C to 100°C

Junction Temperature Range . . . . . . . . . . . . . . . 0

°C to 150°C

θ

JA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

°C/W

Storage Temperature Range . . . . . . . . . . . . –65

°C to +150°C

Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . 300

°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

ORDERING GUIDE

Temperature

Package

Package

Model

Range

Description

Option

ADP3421JRU 0

°C to 100°C

Thin Shrink Small RU-28

Outline (TSSOP)

PIN CONFIGURATION

TOP VIEW

(Not to Scale)

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

2

3

4

5

6

7

8

9

10

11

12

13

14

ADP3421

IOFB

IODRV

CLKFB

CLKDRV

VID0

VID1

VID2

VHYS

CLSET

LTO

LTI

VID3

VID4

LTB

SD

PWRGD

UVLO

SSC

CORE

DACOUT

CS–

CS+

REG

GND

OUT

VCC

SSL

RAMP

PIN FUNCTION DESCRIPTIONS

Pin

Mnemonic

Function

1

VHYS

Core Comparator Hysteresis Setting. The voltage at this pin is held at a 1.7 V reference level. A resistor to

ground programs at a 1:1 ratio the current that is alternately switched into and out of the RAMP pin.

2

CLSET

Current Limit Setting. The voltage at this pin is held at a 1.7 V reference level. A resistor to ground programs

a current that is gained up by 3:1 flowing out of the CS– pin, assuming the current limit comparator is not

triggered.

3

LTO

Level Translator Output. This pin must be tied through a pull-up resistor to the voltage level desired for the

output high level. That voltage cannot be less than 1.5 V.

4

LTI

Level Translator Input. This pin should be driven from an open drain/collector signal. The pull-up current is

provided by the pull-up resistor on the LTO pin. However, the pull-up current will be terminated when the

LTI pin reaches 1.5 V.

5

LTB

Level Translator Bypass. For operation of the level translator with high-speed signals, this pin should be by-

passed to ground with a large value capacitor.

6

VID4

VID Input. Most significant bit.

7

VID3

VID Input

8

VID2

VID Input

9

VID1

VID Input

10

VID0

VID Input. Least significant bit.

11

CLKDRV

2.5 V Linear Regulator Driver Output. This pin sinks current from the base of a PNP transistor as needed to

keep the CLKFB node regulated at 2.5 V.

12

CLKFB

2.5 V Linear Regulator Output Feedback. This pin is connected to the collector of a PNP transistor whose

base is driven by the CLKDRV pin.

13

IODRV

1.5 V Linear Regulator Driver Output. This pin sinks current from the base of a PNP transistor as needed to

keep the IOFB node regulated at 1.5 V.

14

IOFB

1.5 V Linear Regulator Output Feedback. This pin is connected to the collector of a PNP transistor whose

base is driven by the IODRV pin.