REV. A

ADP3421

–11–

Power Switching Circuitry

ADP3410, MOSFETs, Input Capacitors

3. Locate the ADP3410 near the MOSFETs so the parasitic

inductance in the gate drive traces and the trace to the SW

pin is small, and so that the ground pins of the ADP3410

are closely connected to the lower MOSFET’s source.

4. Locate at least one substantial (i.e., > ~1

µF) input bypass

MLC capacitor close to the MOSFETs so that the physical

area of the loop enclosed in the electrical path through the

bypass capacitor and around through the top and bottom

MOSFETs (drain-source) is small. This is the switching

power path loop.

5. Make provisions for thermal management of all the MOSFETs.

Heavy copper and wide traces to ground and power planes will

help to pull out the heat. Heat sinking by a metal tap soldered

in the power plane near the MOSFETs will help. Even just

small airflow can help tremendously. Paralleled MOSFETs will

help spread the heat, even if the on resistance is higher.

6. An external “antiparallel” Schottky diode (across the bottom

MOSFET) may help efficiency a small amount (< ~1 %); a

MOSFET with a built-in antiparallel Schottky is more

effective. For an external Schottky, it should be placed next

to the bottom MOSFET or it may not be effective at all.

Also, a higher current rating (bigger device with lower voltage

drop) is more effective.

7. Both ground pins of the ADP3410 should be connected into

the same ground plane with the power switching circuitry,

and the VCC bypass capacitor should be close to the VCC

pin and connected into the same ground plane.

Output Filter

Output Inductor and Capacitors, Current-Sense Resistor

8. Locate the current-sense resistor very near to the output

capacitors.

9. PCB trace resistances from the current-sense resistor to the

output capacitors, and from the output capacitors to the

load, should be minimized, known (calculated or measured),

and compensated for as part of the design if it is significant.

(Remote sensing is not sufficient for relieving this require-

ment.) A square section of 1 ounce copper trace has a

resistance of ~500 m

Ω. Using 2~3 squares of copper can

make a noticeable impact on a 15 A design.

10. Whenever high currents must be routed between PCB layers,

vias should be used liberally to create several parallel current

paths so that the resistance and inductance introduced by

these current paths is minimized and the via current rating

is not exceeded.

11. The ground connection of the output capacitors should be

close to the ground connection of the lower MOSFET and

it should be a ground plane. Current may pulsate in this

path if the power source ground is closer to the output

capacitors than the power switching circuitry, so a close

connection will minimize the voltage drop.

Control Circuitry

ADP3421, Control Components

12. If the placement overview cannot be followed, the ground

pin of the ADP3421 should be Kelvin-connected into the

ground plane near the output capacitors to avoid introduc-

ing ground noise from the power switching stage into the

control circuitry. All other control components should be

grounded on that same signal ground.

13. If critical signal lines (i.e., signals from the current-sense

resistor leading back to the ADP3421) must cross through

power circuitry, it is best if a signal ground plane can be

interposed between those signal lines and the traces of the

power circuitry. This serves as a shield to minimize noise

injection into the signals at the expense of making signal

ground a bit noisier.

14. Absolutely avoid crossing any signal lines over the switching

power path loop, as previously described.

15. Accurate voltage positioning depends on accurate current

sensing, so the control signals that differentially monitor

the voltage across the current-sense resistor should be

Kelvin-connected.

16. The RC filter used for the current-sense signal should be

located near the control components.

LDOs

PNP Transistors

17. The maximum steady-state power dissipation expected

for the design should be calculated so that an acceptable

package type PNP for each output is selected and properly

mounted to be able to dissipate the power with acceptable

temperature rise.

18. Each PNP transistor should be located close to the load that

it sources.

19. The supply voltage to the PNP emitters should be low

impedance to avoid loop instability. It is good design practice

to have at least one MLC capacitor near each of the PNP

emitters to help ensure the impedance is sufficiently low.