REV. A

ADP3421

–5–

Pin

Mnemonic

Function

15

SD

Shutdown Input. When this pin is pulled low, the IC shuts down and all regulation functions will be disabled.

16

PWRGD

Power Good Output. This signal will go high only when the

SD pin is high to allow IC operation, the UVLO

and VCC pins are above their respective start-up thresholds, the SSC and SSL pins are above a voltage where

soft start is completed, and the voltage at the CORE pin is within the specified limits of the programmed VID

voltage. By choosing the soft-start capacitor for the core larger than that for the linear regulators, at start-up

the core and linear outputs should all be in regulation before PWRGD is asserted.

17

UVLO

Undervoltage Lockout Input. This pin monitors the input voltage through a resistor divider. When the pin

voltage is below a specified threshold, the IC enters into UVLO mode regardless of the status of

SD. When

in UVLO mode, a current source is switched on at this pin, which sinks current from the external resistor

divider. The generated UVLO hysteresis is equal to the current sink value times the upper divider resistor.

18

SSL

Linear Regulator Soft Start. During power-up, an external soft-start capacitor is charged by a current source

to control the ramp-up rates of the linear regulators.

19

SSC

Core Voltage Soft Start. During power-up, an external soft-start capacitor is charged by a current source to

control the ramp-up rate of the core voltage.

20

CORE

Core Converter Voltage Monitor. This pin is used to monitor the core voltage for power good verification.

21

DACOUT

VID-Programmed Digital-to-Analog Converter Output. This voltage is the reference voltage for output

voltage regulation.

22

GND

Ground

23

OUT

Logic-Level Drive Signal Output of Core Controller. This pin provides the drive command signal to the IN

pin of the ADP3410 driver. This pin is not capable of directly driving a power MOSFET.

24

VCC

Power Supply

25

RAMP

Current Ramp Input. This pin provides the negative feedback for the core output voltage. The switched sink/

source current from this pin, which is set up at the VHYS pin, works against the terminating resistance at this

pin to set the hysteresis for the hysteretic control.

26

REG

Regulation Voltage Summing Input. In the recommended configuration, the DACOUT voltage and the core

voltage are summed at this pin to establish regulation with output voltage positioning.

27

CS+

Current Limit Positive Sense. This pin senses the positive node of the current sense resistor.

28

CS–

Current Limit Negative Sense. This pin connects through a resistor to the negative node of the current sense

resistor. A current flows out of the pin, as programmed at the CLSET pin. When this pin is more negative

than the CS+ pin, the current limit comparator is triggered and the current flowing out of the pin is reduced

to two-thirds of its previous value, producing a current limit hysteresis.