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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DP83901AV датащи(PDF) 45 Page - National Semiconductor (TI) |
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DP83901AV датащи(HTML) 45 Page - National Semiconductor (TI) |
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45 / 62 page  130 Bus Arbitration and Timing (Continued) SLAVE MODE TIMING When CS is low the SNIC becomes a bus slave The CPU can then read or write any internal registers All register access is byte wide The timing for register access is shown below The host CPU accesses internal registers with four address lines RA0 – RA3 SRD and SWR strobes ADS0 is used to latch the address when interfacing to a multiplexed address data bus Since the SNIC may be a local bus master when the host CPU attempts to read or write to the controller an ACK line is used to hold off the CPU until the SNIC leaves master mode Some number of BSCK cycles is also required to allow the SNIC to synchro- nize to the read or write cycles Write to Register TLF10469 – 30 Read from Register TLF10469 – 31 TIME BETWEEN CHIP SELECTS The SNIC requires that successive chip selects be no closer than 4 bus clocks (BSCK) together If the condition is violat- ed the SNIC may glitch ACK CPUs that operate from pipe- lined instructions (ie 386) or have a cache (ie 486) can execute consecutive IO cycles very quickly The solution is to delay the execution of consecutive IO cycles by either breaking the pipeline or forcing the CPU to access outside its cache Time between Chip Selects TLF10469 – 58 45 |
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