DP83901AV datasheet(44/62 Pages) NSC

44 / 62 page

130 Bus Arbitration and Timing (Continued)

TLF10469 – 57

Note

The dashed lines indicate incorrect timing as described in the text

FIGURE 9 Timing Diagram for Dummy Remote Read

Write operation could be corrupted This is shown by the

hatched waveforms in the timing diagram of

Figure 9 The

execution of the Remote Read can be delayed by the local

DMA operations (particularly during end-of-packet process-

ing)

To ensure the dummy Remote Read does execute a delay

must be inserted between writing the Remote Read Com-

mand and starting to write the Remote Write State Address

(This time is designated in

Figure 9 by the delay arrows)

The recommended method to avoid this problem is after the

Remote Read command is given to poll both bytes of the

Current Remote DMA Address Registers When the ad-

dress has incremented PRQ has been set Software should

recognize this and then start the Remote Write

An additional caution for high speed systems is that the

polling must follow guidelines specified in Time Between

Chip Select section That is there must be at least 4 bus

clocks between chip selects (for example when BSCK e 20

MHz then this time should be 200 ns)

The general flow for executing a Remote Write is

1 Set Remote Byte Count to a value l1 and Remote Start

Address to unused RAM (one location before the transmit

start address is usually a safe location)

2 Issue the ‘‘dummy’’ Remote Read command

3 Read the Current Remote DMA Address (CRDA) (both

bytes)

4 Compare to previous CRDA value if different go to 6

5 Delay and jump to 3

6 Set up for the Remote Write command by setting the

Remote Byte Count and the Remote Start Address (note

that if Remote Byte count in step 1 can be set to the

transmit byte count plus one and the Remote Start Ad-

dress to one less these will now be incremented to the

correct values)

7 Issue the Remote Write command

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