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CDCVF2310MPWREP датащи(PDF) 7 Page - Texas Instruments

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номер детали CDCVF2310MPWREP
подробное описание детали  2.5-V TO 3.3-V HIGH-PERFORMANCE CLOCK BUFFER
PDF  16 Pages
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CDCVF2310MPWREP датащи(HTML) 7 Page - Texas Instruments

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CLK
Gn
Yn
tsu(en)
th(en)
CLK
Gn
Yn
tsu(dis)
th(dis)
a) Enable Mode
b) Disable Mode
CDCVF2310-EP
www.ti.com
SCAS934 – DECEMBER 2012
DETAILED DESCRIPTION
Output Enable Glitch Suppression Circuit
The purpose of the glitch suppression circuitry is to ensure the output enable sequence is synchronized with the
clock input such that the output buffer is enabled or disabled on the next full period of the input clock (negative
edge triggered by the input clock) (see Figure 1).
The G input must fulfill the timing requirements (tsu, th) according to the Switching Characteristics table for
predictable operation.
Figure 1. Enable and Disable Mode Relative to CLK
↓
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