CDCVF2310MPWREP datasheet(6/16 Pages) TI1

6 / 16 page

CDCVF2310-EP

SCAS934 – DECEMBER 2012

www.ti.com

TIMING REQUIREMENTS

over recommended ranges of supply voltage and operating junction temperature

MIN NOM

MAX

UNIT

VDD = 3 V to 3.6 V

200

fclk

Clock frequency

MHz

VDD = 2.3 V to 2.7 V

170

JITTER CHARACTERISTICS

Characterized using CDCVF2310 Performance EVM when VDD=3.3 V. Outputs not under test are terminated to 50 Ω.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

12 kHz to 5 MHz, fout = 30.72 MHz

tjitter

Additive phase jitter from input to output 1Y0

fs rms

12 kHz to 20 MHz, fout = 125 MHz

SWITCHING CHARACTERISTICS

over recommended operating junction temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VDD = 3.3 V ±0.3 V (see Figure 2)

tPLH

f = 0 MHz to 200 MHz

CLK to Yn

1.3

3.3

For circuit load, see Figure 2.

tPHL

tsk(o)

Output skew (Ym to Yn) (1) (see Figure 4)

100

tsk(p)

Pulse skew (see Figure 5)

570

tsk(pp)

Part-to-part skew

500

Rise time (see Figure 3)

VO = 0.4 V to 2 V

0.7

2.2

V/ns

Fall time (see Figure 3)

VO = 2 V to 0.4 V

0.7

2.2

V/ns

tsu(en)

Enable setup time, G_high before CLK

↓

0.1

tsu(dis)

Disable setup time, G_low before CLK

↓

0.1

th(en)

Enable hold time, G_high after CLK

↓

0.4

th(dis)

Disable hold time, G_low after CLK

↓

0.4

VDD = 2.5 V ±0.2 V (see Figure 2)

tPLH

f = 0 MHz to 170 MHz

CLK to Yn

1.5

For circuit load, see Figure 2.

tPHL

tsk(o)

Output skew (Ym to Yn) (1) (see Figure 4 )

170

tsk(p)

Pulse skew (see Figure 5)

680

tsk(pp)

Part-to-part skew

600

Rise time (see Figure 3)

VO = 0.4 V to 1.7 V

0.5

1.4

V/ns

Fall time (see Figure 3)

VO = 1.7 V to 0.4 V

0.5

1.4

V/ns

tsu(en)

Enable setup time, G_high before CLK

↓

0.1

tsu(dis)

Disable setup time, G_low before CLK

↓

0.1

th(en)

Enable hold time, G_high after CLK

↓

0.4

th(dis)

Disable hold time, G_low after CLK

↓

0.4

(1)

The tsk(o) specification is only valid for equal loading of all outputs.

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