DP8344B datasheet(18/184 Pages) NSC

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20 CPU Description (Continued)

2121 Timer Operation

After the desired 16-bit time-out value is written into TRL

and

TRH

the start load and clock selection can be

achieved in a single write to ACR

A restriction exists on

changing the timer clock frequency in that TCS should not

be changed while the timer is running (ie

TST is high)

After a write to ACR to load and start the timer the timer

begins counting down at the selected frequency from the

value in TRL and TRH

Upon reaching a count of zero

the timer interrupt is generated and the timer reloads the

current word from

TRL

and

TRH

to cycle through a

countdown again The timing waveforms shown in

Figure

2-3 show a write to ACR that loads starts selects the

CPU clock rate2 for the countdown rate and asserts the

Global Interrupt Enable GIE

Prior to the write to ACR

TRL and TRH were loaded with 00h and 01h respec-

tively the timer interrupt was unmasked in the Interrupt

Control Register ICR by clearing bit 4 and zero instruc-

tion wait states were selected in DCR

Since the write to

ACR

asserted GIE

the timer interrupt is enabled and

the CPU will vector to the timer interrupt service routine

address when the timer reaches a count of zero The timer

interrupt is the lowest priority interrupt and is latched and

maintained until it is cleared in software (See CPU Inter-

rupts section) For very long time intervals time-outs can be

accumulated under software control by writing a one to TO

in CCR allowing the timer to recycle its count down with

no other intervention For time-outs attainable with one

count down stopping the timer will clear the interrupt and

When the timer interrupt is enabled the call to the

interrupt service routine occurs at different instruction

boundaries depending on when the timer interrupt occurs in

the instruction cycle If the timer times out prior to T2 where

T2 is the last T-state of an instruction cycle the call to the

interrupt service routine will occur in the next instruction

When the time-out occurs in T2 the call to the interrupt

service routine will not occur in the next instruction It occurs

in the second instruction following T2

The count status of the timer can be monitored by reading

TRL andor TRH

When the registers are read the out-

put of the timer not the value in the input holding registers

is presented to the ALU Some applications might require

monitoring the count status of the timer while it is counting

down Since the timer can time-out between reads of TRL

and TRH

the software should take this fact into consider-

ation To read back what was written to TRL and TRH

the timer must first be loaded via TLD without starting the

timer followed by a one instruction delay before reading

TRL and TRH to allow the output registers to be updat-

ed from the load operation

To determine the time-out delay for a given value in TRL

and TRH other than 0000h the following equation can be

used

TD e(value in TRH

TRL )

where

k e 2 when TCS e 1 or 16 when TCS e 0

T e The period of the CPU clock

TD e The amount of time delay after the end of the in-

struction that asserts TST in ACR

When the value of 0000h is loaded in the timer the maxi-

mum time-out is obtained and is calculated as follows

TD e65536

With the CPU running full speed with an 188 MHz crystal

the maximum single loop time delay attainable would be

556 ms ( TCS e 0) The minimum time delay with the

same constraints is 106 ns ( TCS e 1) For accumulating

time-out intervals the total time delay is simply the number

of loops accumulated multiplied by the calculated time de-

lay The equations above do not account for any overhead

for processing the timer interrupt The added overhead of

processing the interrupt may need to be included for preci-

sion timing

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