DP8344B datasheet(13/184 Pages) NSC

13 / 184 page

20 CPU Description

The CPU is a general purpose 8-bit microprocessor capa-

ble of 20 MHz operation It contains a large register set for

standard CPU operations and control of the transceiver

The reduced instruction set is optimized for the communica-

tions environment The following sections are an architec-

tural and functional description of the DP8344B CPU

21 CPU ARCHITECTURAL DESCRIPTION

211 Register Set

This section describes the BCP’s internal CPU registers It is

a general overview of the register structure and the func-

tions mapped into the CPU register space It is not a de-

tailed or exhaustive description of every bit For such a de-

scription please refer to Section 62 Register Set Refer-

ence Also the Remote Interface Configuration register

RIC

is not accessible to the BCP (being accessible only

by the remote system) and is described in Section 63 Re-

mote Interface Reference

The register set of the BCP provides for a compliment of

both special function and general purpose registers The

special function registers provide access to on-chip periph-

erals (transceiver timer interrupt control etc) while the

general purpose registers maximize CPU throughput by min-

imizing accesses to external data memory The CPU can

address a total of 44 8-bit registers providing access to

20 general purpose registers

8 configuration and control registers

4 transceiver access registers

2 8-bit accumulators

4 16-bit pointers

16-bit timer

16 byte data stack

address and data stack pointers

The CPU addresses internal registers with a 5-bit field ad-

dressing 32 locations generically named R0 through R31

The first twelve locations (R0 – R11) are further organized by

function as two groups of banked registers (A and B) as

shown in

Figure 2-1 Each group contains both a main and

an alternate bank Only one bank is active for group A and

one for bank B and thus accessible during program execu-

tion Switching between the banks is performed by the ex-

change instruction EXX which selects whether Main A or

Alternate A occupies R0 – R3 and whether Main B or Alter-

nate B occupies R4 – R11

TLF9336 – 32

FIGURE 2-1 Register Map

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