DP8344B datasheet(39/184 Pages) NSC

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20 CPU Description (Continued)

TLF9336 – F1

FIGURE 2-28 Three T-state Program Control Instruction WAIT Timing

TLF9336 – F2

FIGURE 2-29 Four T-state Program Control Instruction WAIT Timing

LOCK is another input which affects BCP instruction timing

LOCK prevents the BCP from accessing data memory

When asserted low LOCK will cause the BCP to wait when

it executes a data memory access instruction The BCP will

be waited until LOCK is taken high To prevent a given ac-

cess of data memory LOCK must be asserted low one-half

T-state prior to the beginning of the instruction accessing

data memory

Figure 2-30 shows LOCK being used to wait a

write to data memory LOCK falls prior to the falling edge of

CPU-CLK before T1 In order to guarantee at least one wait

state LOCK is held low until after the falling edge of CPU-

CLK in T1 This causes the insertion of TW into the cycle

prior to TX ALE remains high and the address is delayed on

AD until LOCK is removed After LOCK rises the access

concludes normally with ALE falling halfway through TX and

WRITE occurring during T2 Note that LOCK waits the ac-

cess at a different point in the cycle than programmed wait

states or WAIT Additional wait states could occur from

these sources prior to T2

Figure 2-31 shows an example of

LOCK holding off a write to data memory with one pro-

grammed wait state

With timing similar to LOCK the BCP will be delayed from

making a data memory access by an access from the re-

mote system If the remote system is accessing the Remote

Interface Configuration register

RIC

or data memory the

BCP will be waited by the Remote Interface and Arbitration

System RIAS until the remote access is finished The

length of time the BCP is waited depends on the speed of

the remote system and the type of remote access The wait

states are added prior to TX in the same manner as for

LOCK shown in

Figure 2-30 A more detailed description of

the operation of RIAS can be found in Section 40 Remote

Interface and Arbitration System

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