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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320C6713 датащи(PDF) 21 Page - Texas Instruments |
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TMS320C6713 датащи(HTML) 21 Page - Texas Instruments |
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21 / 150 page  TMS320C6713, TMS320C6713B FLOATING-POINT DIGITAL SIGNAL PROCESSORS SPRS186I − DECEMBER 2001 − REVISED MAY 2004 21 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 peripheral register descriptions (continued) Table 12. McASP0 and McASP1 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME McASP0 McASP1 ACRONYM REGISTER NAME 3C00 0000 − 3C00 FFFF 3C10 0000 − 3C10 FFFF RBUF/XBUFx McASPx receive buffer or McASPx transmit buffer via the Peripheral Data Bus. (Used when RSEL or XSEL bits = 0 [these bits are located in the RFMT or XFMT registers, respectively].) 01B4 C000 01B5 0000 MCASPPIDx Peripheral Identification register [13/13B value: 0x00100101 for McASP0 and for McASP1] 01B4 C004 01B5 0004 PWRDEMUx Power down and emulation management register 01B4 C008 01B5 0008 − Reserved 01B4 C00C 01B5 000C − Reserved 01B4 C010 01B5 0010 PFUNCx Pin function register 01B4 C014 01B5 0014 PDIRx Pin direction register 01B4 C018 01B5 0018 PDOUTx Pin data out register 01B4 C01C 01B5 001C PDIN/PDSETx Pin data in / data set register Read returns: PDIN Writes affect: PDSET 01B4 C020 01B5 0020 PDCLRx Pin data clear register 01B4 C024 − 01B4 C040 01B5 0024 − 01B5 0040 − Reserved 01B4 C044 01B5 0044 GBLCTLx Global control register 01B4 C048 01B5 0048 AMUTEx Mute control register 01B4 C04C 01B5 004C DLBCTLx Digital Loop-back control register 01B4 C050 01B5 0050 DITCTLx DIT mode control register 01B4 C054 − 01B4 C05C 01B5 0054 − 01B5 005C − Reserved 01B4 C060 01B5 0060 RGBLCTLx Alias of GBLCTL containing only Receiver Reset bits, allows transmit to be reset independently from receive. 01B4 C064 01B5 0064 RMASKx Receiver format unit bit mask register 01B4 C068 01B5 0068 RFMTx Receive bit stream format register 01B4 C06C 01B5 006C AFSRCTLx Receive frame sync control register 01B4 C070 01B5 0070 ACLKRCTLx Receive clock control register 01B4 C074 01B5 0074 AHCLKRCTLx High-frequency receive clock control register 01B4 C078 01B5 0078 RTDMx Receive TDM slot 0−31 register 01B4 C07C 01B5 007C RINTCTLx Receiver interrupt control register 01B4 C080 01B5 0080 RSTATx Status register − Receiver 01B4 C084 01B5 0084 RSLOTx Current receive TDM slot register 01B4 C088 01B5 0088 RCLKCHKx Receiver clock check control register 01B4 C08C − 01B4 C09C 01B5 008C − 01B5 009C − Reserved 01B4 C0A0 01B5 00A0 XGBLCTLx Alias of GBLCTL containing only Transmitter Reset bits, allows transmit to be reset independently from receive. 01B4 C0A4 01B5 00A4 XMASKx Transmit format unit bit mask register 01B4 C0A8 01B5 00A8 XFMTx Transmit bit stream format register 01B4 C0AC 01B5 00AC AFSXCTLx Transmit frame sync control register 01B4 C0B0 01B5 00B0 ACLKXCTLx Transmit clock control register 01B4 C0B4 01B5 00B4 AHCLKXCTLx High-frequency Transmit clock control register |
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