TMS320C6713 datasheet(86/150 Pages) TI

86 / 150 page

TMS320C6713, TMS320C6713B

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS186I − DECEMBER 2001 − REVISED MAY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

multichannel audio serial port (McASP) peripherals (continued)

McASP flexible clock generators

The McASP transmit and receive clock generators are identical. Each clock generator can accept a

high-frequency master clock input (on the AHCLKX and AHCLKR pins).

The transmit and receive bit clocks (on the ACLKX and ACLKR pins) can also be sourced externally or can be

sourced internally by dividing down the high-frequency master clock input (programmable factor /1, /2, /3, ...

/4096). The polarity of each bit clock is individually programmable.

The frame sync pins are AFSX (transmit) and AFSR (receive). A typical usage for these pins is to carry the

left-right clock (LRCLK) signal when transmitting and receiving stereo data. The frame sync signals are

individually programmable for either internal or external generation, either bit or slot length, and either rising or

falling edge polarity.

Some examples of the things that a system designer can use the McASP clocking flexibility for are:

D Input a high-frequency master clock (for example, 512fs of the receiver), receive with an internally

generated bit clock ratio of /8, while transmitting with an internally generated bit clock ratio of /4 or /2. [An

example application would be to receive data from a DVD at 48 kHz but output up-sampled or decoded

audio at 96 kHz or 192 kHz.]

D Transmit/receive data based one sample rate (for example, 44.1 kHz) using McASP0 while transmitting and

receiving at a different sample rate (for example, 48 kHz) on McASP1.

D Use the DSP’s on-board AUXCLK to supply the system clock when the input source is an A/D converter.

McASP error handling and management

To support the design of a robust audio system, the McASP module includes error-checking capability for the

serial protocol, data underrun, and data overrun. In addition, each McASP includes a timer that continually

measures the high-frequency master clock every 32-SYSCLK2 clock cycles. The timer value can be read to

get a measurement of the high-frequency master clock frequency and has a min-max range setting that can

raise an error flag if the high-frequency master clock goes out of a specified range. The user would read the

high-frequency transmit master clock measurement (AHCLKX0 or AHCLKX1) by reading the XCNT field of the

XCLKCHK register and the user would read the high-frequency receive master clock measurement (AHCLKR0

or AHCLKR1) by reading the RCNT field of the RCLKCHK register.

Upon the detection of any one or more of the above errors (software selectable), or the assertion of the

AMUTE_IN pin, the AMUTE output pin may be asserted to a high or low level (selectable) to immediately mute

the audio output. In addition, an interrupt may be generated if enabled based on any one or more of the error

sources.

McASP interrupts and EDMA events

The McASP transmitter and receiver sections each generate an event on every time slot. This event can be

serviced by an interrupt or by the EDMA controller.

When using interrupts to service the McASP, each shift register buffer has a unique address in the McASP

Registers space (see Table 3).

When using the EDMA to service the McASP, the McASP DATA Port space in Table 3 is accessed. In this case,

the address least-significant bits are ignored. Writes to any address in this range access the transmitting buffers

in order from lowest (serializer 0) to highest (serializer 15), skipping over disabled and receiving serializers.

Likewise, reads from any address in this space access the receiving buffers in the same order but skip over

disabled and transmitting buffers.

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