OPA657

14

SBOS197B

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Capacitive Load and the resulting frequency response at the

load. In this case, a design target of a maximally flat fre-

if some peaking can be tolerated. Also, operating at higher

gains (than the +10 used in the Typical Characteristics) will

response. Parasitic capacitive loads greater than 2pF can

begin to degrade the performance of the OPA657. Long PC

board traces, unmatched cables, and connections to multiple

devices can easily cause this value to be exceeded. Always

consider this effect carefully, and add the recommended

series resistor as close as possible to the OPA657 output pin

(see Board Layout section).

DISTORTION PERFORMANCE

The OPA657 is capable of delivering a low distortion signal

at high frequencies over a wide range of gains. The distortion

plots in the Typical Characteristics show the typical distortion

under a wide variety of conditions.

Generally, until the fundamental signal reaches very high

frequencies or powers, the 2nd-harmonic will dominate the

distortion with negligible 3rd-harmonic component. Focusing

then on the 2nd-harmonic, increasing the load impedance

improves distortion directly. Remember that the total load

includes the feedback network—in the non-inverting configu-

increases harmonic distortion directly. A 6dB increase in

output swing will generally increase the 2nd-harmonic 12dB

and the 3rd-harmonic 18dB. Increasing the signal gain will also

increase the 2nd-harmonic distortion. Again a 6dB increase in

gain will increase the 2nd- and 3rd-harmonic by about 6dB

even with a constant output power and frequency. And finally,

the distortion increases as the fundamental frequency in-

creases due to the rolloff in the loop gain with frequency.

Conversely, the distortion will improve going to lower frequen-

cies down to the dominant open loop pole at approximately

100kHz. Starting from the –70dBc 2nd-harmonic for a 5MHz,

2Vp-p fundamental into a 200

Ω load at G = +10 (from the

Typical Characteristics), the 2nd-harmonic distortion for fre-

quencies lower than 100kHz will be approximately < –90dBc.

The OPA657 has an extremely low 3rd-order harmonic distor-

tion. This also shows up in the 2-tone 3rd-order intermodulation

spurious (IM3) response curves. The 3rd-order spurious levels

are extremely low (< –80dBc) at low output power levels. The

output stage continues to hold them low even as the fundamen-

tal power reaches higher levels. As the Typical Characteristics

show, the spurious intermodulation powers do not increase as

predicted by a traditional intercept model. As the fundamental

power level increases, the dynamic range does not decrease

significantly. For 2 tones centered at 10MHz, with 4dBm/tone

into a matched 50

Ω load (i.e., 1Vp-p for each tone at the load,

which requires 4Vp-p for the overall 2-tone envelope at the

output pin), the Typical Characteristics show a 82dBc difference

between the test tone and the 3rd-order intermodulation spuri-

ous levels. This exceptional performance improves further when

operating at lower frequencies and/or higher load impedances.

D.C. ACCURACY AND OFFSET CONTROL

The OPA657 can provide excellent DC accuracy due to its high

open-loop gain, high common-mode rejection, high power-supply

rejection, and its trimmed input offset voltage (and drift) along with

the negligible errors introduced by the low input bias current. For

the best DC precision, a high-grade version (OPA657UB or

OPA657NB) screens the key DC parameters to an even tighter

limit. Both standard- and high-grade versions take advantage of

a new final test technique to 100% test input offset voltage drift

over temperature. This discussion will use the high-grade typical

and min/max electrical characteristics for illustration, however, an

identical analysis applies to the standard-grade version.

The total output DC offset voltage in any configuration and

temperature will be the combination of a number of possible error

terms. In a JFET part like the OPA657, the input bias current

terms are typically quite low but are unmatched. Using bias

current cancellation techniques, more typical in bipolar input

amplifiers, does not improve output DC offset errors. Errors due

to the input bias current will only become dominant at elevated

temperatures. The OPA657 shows the typical 2X increase in

every 10

°C common to JFET-input stage amplifiers. Using the

5pA maximum tested value at 25

°C, and a 20°C internal self

heating (see thermal analysis), the maximum input bias current

at 85

noninverting configurations, this term only begins to be a signifi-

cant term versus the input offset voltage for source impedances

> 750k

Ω. This would also be the feedback resistor value for

transimpedance applications (Figure 3) where the output DC

error due to inverting input bias current is on the order of that

contributed by the input offset voltage. In general, except for

these extremely high-impedance values, the output DC errors

due to the input bias current may be neglected.

After the input offset voltage itself, the most significant term

contributing to output offset voltage is the PSRR for the negative

supply. This term is modeled as an input offset voltage shift due

to changes in the negative power supply voltage (and similarly for

the +PSRR). The high-grade test limit for –PSRR is 68dB. This

low sensitivity to the negative supply voltage would require a 1.5V

change in the negative supply to match the

±0.6mV input offset

voltage error. The +PSRR is tested to a minimum value of 78dB.

offset voltage to positive power-supply changes.

As an example, compute the worst-case output DC error for the

transimpedance circuit of Figure 3 at 25

°C and then the shift

over the 0

°C to 70°C range given the following assumptions.

Negative Power Supply

= –5V

±0.2V with a ±5mV/°C worst-case shift

Positive Power Supply

= +5V

±0.2V with a ±5mV/°C worst-case shift

Initial 25

°C Output DC Error Band

=

±0.6mV (OPA657 high-grade input offset voltage limit)

±0.08mV (due to the –PSRR = 0.4mV/V • ±0.2V)

±0.04mV (due to the +PSRR = 0.2mV/V • ±0.2V)

Total =

±0.72mV