AD8330 datasheet(21/28 Pages) AD

21 / 28 page

REV. A

AD8330

–21–

1.2

05ns

10ns

15ns

25ns

20ns

1.0

0.8

0.6

0.4

0.2

–0.2

0.2

–0.4

–0.6

–0.8

–1.0

–1.2

–0.2

1.2

1.0

0.8

0.6

0.4

0.2

–0.2

0.2

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

Figure 19. Typical Pulse Responses for Figure 18

Figure 19 shows typical results for VDBS = 0.24 V, a square wave

input amplitude of 450 mV (the actual combination is not impor-

tant) and a rise time of 2 ns. VMAG raised to 2.0 V is used. In the

upper waveforms the load capacitors are both zero, and a small

amount of overshoot is visible; with 40 pF the response is cleaner.

A shunt capacitance of 20 pF from OPHI to OPLO will have a

similar effect. Coupling capacitors for this demonstration are

sufficiently large to prevent any visible droop over this time scale.

The outputs at the load side will eventually assume a mean value

of zero, with negative and positive excursions depending on the

duty-cycle.

The bandwidth from pin VMAG to these outputs is somewhat

higher than that from the normal input pins. Thus when this pin

is used to rapidly modulate the primary signal, some further

experimentation with response optimization may be required. In

general, the AD8330 is very tolerant of a wide range of loading

conditions.

Preserving Absolute Gain

Although the AD8330 is not laser-trimmed, its absolute gain cali-

bration, being based mainly on ratios, is very good. Full details can

be found in the Specifications and in the typical performance

curves. Nevertheless, having finite input and output impedances,

the gain is necessarily dependent on the source and load condi-

tions. The loss incurred when either of these is finite causes an

error in the absolute gain, which may also be uncertain due to

the approximately

±20% tolerance in the absolute value of the

input and output impedances.

Often, such losses and uncertainties can be tolerated and accom-

modated by a correction to the gain control bias. On the other

hand, the error in the loss can be essentially nulled by using

appropriate modifications to either the source impedance (RS)

or the load impedance (RL), or both, in some cases by padding

them with series or shunt components.

The formulation for this correction technique was described

previously. However, to simplify its use, Table I is provided, showing

spot values for combinations of RS and RL resulting in an overall

loss that will not be dependent on sample-to-sample variations

in on-chip resistances. Furthermore, this fixed and predictable loss

can be corrected by an adjustment to VMAG, as indicated in Table 1.

Table I. Preserving Absolute Gain

Uncorrected LossVMAG Required

RS(

Ω)R

Ω)

Factor

to Correct Loss

15k

0.980

0.17

0.510

10k

0.971

0.26

0.515

7.5k

0.961

0.34

0.520

5.0k

0.943

0.51

0.530

3.0k

0.907

0.85

0.551

2.0k

0.865

1.26

0.578

100

1.5k

0.826

1.66

0.605

150

1.0k

0.756

2.43

0.661

200

750

0.694

3.17

0.720

300

500

0.592

4.56

0.845

500

300

0.444

7.04

1.125

750

200

0.327

9.72

1.531

150

0.250

12.0

2.000

1.5k

100

0.160

15.9

3.125

0.111

19.1

4.500

Calculation of Noise Figure

The AD8330 noise is a consequence of its intrinsic voltage-noise-

spectral-density (ENSD) and the current-noise-spectral-density

(INSD). Their combined effect generates a net input noise, VNOISE_IN,

which is a function of the device’s input resistance, RI, nominally

1 k

Ω, and the differential source resistance, RS, as follows:

VNOISE_IN =+

()

{}

NSD

(16)

Note that we assume purely resistive source and input impedances

as a concession to simplicity. A more thorough treatment of noise

mechanisms, for the case where the source is reactive, is beyond the

scope of these brief notes. Also note that VNOISE_IN is the voltage-

noise-spectral-density appearing across the differential input pins,

INHI, INLO. In preparing for the calculation of noise figure,

we will define VSIG as the open-circuit signal voltage across the

source and VIN as the differential input to the AD8330. The

relationship is simply

VIN =

()

SIG

(17)

At maximum gain, ENSD is 4.1 nV/

√Hz, and I

NSD is 3 pA/

√Hz.

Thus, the short-circuit voltage noise is:

VNOISE_IN =

() +() Ω+

()













= 508

(18)

Next, examine the net noise when RS = RI = 1 k

Ω, often incorrectly

called the “matching” condition, rather than “source impedance

termination,” which is the actual situation in this case. Repeating

the procedure:

VNOISE_IN =

() +() Ω+ Ω

()













≈ 73

(19)

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