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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD8330 датащи(PDF) 2 Page - Analog Devices |
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AD8330 датащи(HTML) 2 Page - Analog Devices |
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2 / 28 page  REV. A –2– AD8330–SPECIFICATIONS (VS = 5 V, TA = 25 C, CL = 12 pF on OPHI and OPLO, RL = 0/C, VDBS = 0.75 V, VMODE = HI, VMAG = 0/C, VOFST = 0 V, Differential Operation, unless otherwise noted.) Parameter Conditions Min Typ Max Unit INPUT INTERFACE Pins INHI, INLO Full-Scale Input VDBS = 0 V, Differential Drive ±1.4 ±2V VDBS = 1.5 V ±4.5 ±6.3 mV Input Resistance Pin-to-Pin 800 1K 1.2K Ω Input Capacitance Either Pin to COMM 4 pF Voltage Noise Spectral Density f = 1 MHz, VDBS = 1.5 V; 5 nV/ √Hz Inputs AC-shorted Common-Mode Voltage Level 3.0 V Input Offset Pin OFST Connected to COMM 1 mV rms Drift 2 µV/°C Permissible CM Range 1 0VS V Common-Mode AC Rejection f = 1 MHz, 0.1 V rms –60 dB f = 50 MHz –55 dB OUTPUT INTERFACE Pins OPHI, OPLO Small Signal –3dB Bandwidth 0 V < VDBS < 1.5 V 150 MHz Peak Slew Rate VDBS = 0 1500 V/ µs Peak-to-Peak Output Swing ±1.8 ±2 ±2.2 V VMAG ≥ 2 V (Peaks are Supply Limited) ±4 ±4.5 V Common-Mode Voltage Pin CNTR O/C 2.4 2.5 2.6 V Voltage Noise Spectral Density f = 1 MHz, VDBS = 0 62 nV/ √Hz Differential Output Impedance Pin-to-Pin 120 150 180 Ω HD2 2 VOUT = 1 V p-p, f = 10 MHz, RL = 1 k Ω –62 dBc HD3 2 VOUT = 1 V p-p, f = 10 MHz, RL = 1 k Ω –53 dBc OUTPUT OFFSET CONTROL Pin OFST AC-Coupled Offset CHPF on Pin OFST (0 V< VDBS < 1.5 V) 10 mV rms High-Pass Corner Frequency CHPF = 3.3 nF, from OFST 100 kHz to CNTR (Scales as 1/CHPF) COMMON-MODE CONTROL Pin CNTR Usable Voltage Range 0.5 4.5 V Input Resistance From Pin CNTR to VS/2 4 k Ω DECIBEL GAIN CONTROL Pins VDBS, CMGN, MODE Normal Voltage Range CMGN Connected to COMM 0 to 1.5 V Elevated Range CMGN O/C (VCMGN Rises to 0.2 V) 0.2 to 1.7 V Gain Scaling Mode HIGH or LOW 27 30 33 mV/dB Gain Linearity Error 0.3 V ≤ VDBS ≤ 1.2 V –0.35 ±0.1 +0.35 dB Absolute Gain Error VDBS = 0 –2 ±0.5 +2 dB Bias Current Flows out of pin VDBS 100 nA Incremental Resistance 100 M Ω Gain Settling Time to 0.5 dB error VDBS Stepped from 0.05 V–1.45 V 250 ns or 1.45 V–0.05 V Mode Up/Down Pin MODE Mode Up Logic Level Gain Increases with VDBS, MODE = O/C 1.5 V Mode Down Logic Level Gain Decreases with VDBS 0.5 V LINEAR GAIN INTERFACE Pins VMAG, CMGN Peak Output Scaling, Gain vs. VMAG See Circuit Description Section 3.8 4.0 4.2 V/V Gain Multiplication Factor vs. VMAG Gain is Nominal when VMAG = 0.5 V 2 Usable Input Range 0 5 V Default Voltage VMAG O/C 0.48 0.5 0.52 V Incremental Resistance 4k Ω Bandwidth For VMAG ≥ 0.1 V 150 MHz |
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