AD8330 datasheet(13/28 Pages) AD

13 / 28 page

REV. A

AD8330

–13–

CIRCUIT DESCRIPTION

Many monolithic variable-gain amplifiers use techniques that share

common principles that are broadly classified as translinear, a

term referring to circuit cells whose functions depend directly on

the very predictable properties of bipolar junction transistors,

notably the linear dependence of their transconductance on collec-

tor current. Since the discovery of these cells in 1967, and their

commercial exploitation in products developed during the early 1970s,

accurate wide bandwidth analog multipliers, dividers, and variable-

gain amplifiers have invariably employed translinear principles.

While these techniques are well understood, the realization of a

high performance variable-gain amplifier (VGA) requires special

technologies and attention to many subtle details in its design.

The AD8330 is fabricated on a proprietary silicon-on-insulator,

complementary bipolar IC process and draws on decades of

experience in developing many leading-edge products using trans-

linear principles to provide an unprecedented level of versatility.

Figure 2 shows a basic representative cell comprising just four

transistors. This, or a very closely related form, is at the heart of most

translinear multipliers, dividers, and VGAs. The key concepts

are as follows: First, the ratio of the currents in the left-hand and

right-hand pairs of transistors are identical; this is represented

by the modulation factor, x, which may have values between –1

and +1. Second, the input signal is arranged to modulate the fixed

tail current ID to cause the variable value of x introduced in the

left-hand pair to be replicated in the right-hand pair, and thus

generate the output by modulating its nominally fixed tail current

IN. Third, the current-gain of this cell is very exactly G = IN/ID

over many decades of variable bias current. In practice, the

realization of the full potential of this circuit involves many other

factors, but these three elementary ideas remain essential.

By varying IN, the overall function is that of a two-quadrant

analog multiplier, exhibiting a linear relationship to both the signal

modulation factor x and this numerator current. On the other

hand, by varying ID, a two-quadrant analog divider is realized,

having a hyperbolic gain function with respect to the input

factor x, controlled by this denominator current. The AD8330

exploits both modes of operation. However, since a hyperbolic

gain function is generally of less value than one in which the

decibel gain is a linear function of a control input, a special interface

is included to provide either increasing or decreasing exponential

control of ID.

INPUT IS xlD

DENOMINATOR

BIAS CURRENT

(1–x) ID

+–

LOOP

AMPLIFIER

(1–x) IN

NUMERATOR

BIAS CURRENT

OUTPUT IS xlN

G = IN/ID

(1+x) IN

(1–x) ID

Figure 2. The Basic Core of the AD8330

COMM

OPHI

INLO

OPLO

INHI

VPSI

VPSO

CMOP

MODE

VDBS

CMGN

VMAG

OFST

ENBL

CNTR

VPOS

BIAS AND

VREF

GAIN INTERFACE

CM MODE AND

OFFSET CONTROL

OUTPUT

STAGES

OUTPUT

CONTROL

VGA CORE

AD8330

Figure 3. Block Schematic of the AD8330

Overall Structure

Figure 3 shows a block schematic of the AD8330 in which the key

sections are located. More detailed discussions of its structure

and features are provided later; this figure provides a general

overview of its capabilities.

The VGA core contains a much elaborated version of the cell shown

in Figure 2. The current called ID is controlled exponentially

(linear in decibels) through the decibel gain interface at the pin

VDBS and its local common CMGN. The gain span (that is,

the decibel difference between maximum and minimum values)

provided by this control function is slightly more than 50 dB.

The absolute gain from input to output is a function of source

and load impedance and also depends on the voltage on a second

gain-control pin, VMAG, as will be explained in a moment.

Normal Operating Conditions

To minimize confusion, we define these normal operating condi-

tions: the input pins are voltage driven (the source impedance is

assumed to be zero); the output pins are open circuited (the load

impedance is assumed to be infinite); pin VMAG is unconnected,

which sets up the output bias current (IN in the four-transistor gain

cell) to its nominal value; pin CMGN is grounded; and MODE

is either tied to a logic high or left unconnected, to set the UP

gain mode. The effects of other operating conditions can then be

considered separately.

Throughout this data sheet, the end-to-end voltage gain for the

normal operating conditions will be referred to as the Basic

Gain. Under these conditions, it runs from 0 dB when VDBS = 0

(where this voltage is more exactly measured with reference to

pin CMGN, which may not necessarily be tied to ground) up to

50 dB for VDBS = 1.5 V. The gain does not “fold-over” when

the VDBS pin is driven below ground or above its nominal full-

scale value.

The input is accepted at the differential port INHI/INLO. These

pins are internally biased to roughly the midpoint of the supply

VS (it is actually ~2.75 V for VS = 5 V, VDBS = 0, and 1.5 V for VS

= 3 V), but the AD8330 is able to accept a forced common-

mode value, from zero to VS, with certain limitations. This interface

provides good common-mode rejection up to high frequencies

(see TPC 13) and thus can be driven in either a single-sided or

differential manner. However, operation using a differential drive

is preferable, and this is assumed in the specifications, unless

otherwise stated.

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