RT9451

26

DS9451-00

September 2013

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Interrupt MASK Register 2 (MASK2)

Address - 0x0Ch

Data

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Field

Name

CHRVPM

CHBADM

CHBATOVM CHTERMM CHRCHGM

CH32MM CHTREGM CHMIVRM

Read/

Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

Value

0

0

0

0

0

0

0

0

Field Name

Bit Definition

(1)

CHRVPM

Charger reverse protection interrupt mask

0 – Interrupt not masked

1 – Interrupt masked

CHBADM

Charger Bad adaptor interrupt mask

0 – Interrupt not masked

1 – Interrupt masked

CHBATOVM

Charger battery over voltage interrupt mask

0 – Interrupt not masked

1 – Interrupt masked

CHTERMM

Charge terminated interrupt mask

0 – Interrupt not masked

1 – Interrupt masked

CHRCHGM

Charger recharge request interrupt mask

0 – Interrupt not masked

1 – Interrupt masked

CH32MM

Charger 32m timeout interrupt mask

0 – Interrupt not masked

1 – Interrupt masked

CHTREGM

Charger thermal regulation loop active interrupt mask

0 – Interrupt not masked

1 – Interrupt masked

CHMIVRM

Charger input current MIVR active interrupt mask

0 – Interrupt not masked

1 – Interrupt masked

(1) Setting any of the interrupt mask bits does not disable protection circuits. When set, the respective fault will not be

signaled on the INT pin.