RV-3049 datasheet(49/65 Pages) MICROCRYSTAL

49 / 65 page

Micro Crystal

DTCXO Temperature Compensated Real Time Clock / Calendar Module

RV-3049

49/65

6.2. SPI INTERFACE DATA TRANSMISSION

The data transmission is controlled by the active HIGH chip enable signal CE. The data transfer is initiated by the

Master by raising the chip enable signal CE of the considered Slave device to “1”.

At the beginning of SPI bus data transmission, a copy of the content of the addressed Watch, Alarm, Timer and

Temperature registers is stored into a cache memory. During read / write operation, data are provided from this

cache memory.

To prevent faulty reading, data in the cache memory are kept stable until the SPI bus data transmission is

terminated. When the Master is pulling the CE to “0”, the content of the modified registers in the cache memory are

copied back into the corresponding Watch, Alarm, Timer and Temperature registers.

Each data transfer is a byte, with the Most Significant Bit (MSB) sent first. The first byte transmitted is the

Command Byte, defining the address of the first register to be accessed and the read or write mode.

One data bit is transferred during each SCL clock pulse. Data are sampled on the rising edge of the SCL clock and

internally transferred on the falling edge of the SCL clock. In idle mode, SCL shall be LOW.

The register address (within the same page) will automatically increment after transmission of every byte. The page

address remains unchanged until data transfer is stopped and a new data transfer is initiated. Therefore, CE must

return LOW before a new data transfer can be executed.

Data transfer is terminated by the Master by pulling the chip enable CE of the addressed Slave device to “0”.

Data Transfer Overview

6.2.1.COMMAND BYTE DEFINITION

Bit

Symbol

Value

Description

R/W

Data read or write selection

Write data; master writes data on the SDI line

Read data; RV-3049 writes data on the SDO line

6 to 3

-0xxx

Page Address; the not transmitted bit 7 of the page address is set internally

to = “0”

2 to 0

000

111

each byte

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