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MB91F528 датащи(PDF) 189 Page - SPANSION

номер детали MB91F528
подробное описание детали  This document states the current technical specifications regarding
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MB91F528 датащи(HTML) 189 Page - SPANSION

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D a t a S h e et
186
MB91F528_DS705-00016-1v0-E, March 28, 2014
CONFIDENTIAL
(4-1-2) Bit setting: SMR: MD2=0, SMR: MD1=1, SMR : MD0=0, SMR: SCINV=1, SCR:SPI=0
(TA: -40°C to +125°C , VCC= AVCC=5.0V ± 10%/VCC=AVCC=3.3V±0.3V,VSS=AVSS=0.0V)
Parameter
Symbol
Pin name
Cond
itions
Value
Unit
Remarks
Min
Max
Serial clock cycle
time
tSCYC
SCK0 to SCK19
-
4tCPP
-
ns
Internal shift clock
mode output pin :
CL=50pF
SCK
↑ →
SOT delay time
tSHOVI
SCK0 to SCK2,
SCK5 to SCK19
SOT0 to SOT2,
SOT5 to SOT19
-30
30
ns
SCK3, SCK4
SOT3, SOT4
-300
300
ns
Valid SIN
→
SCK
↓ setup time
tIVSLI
SCK0 to SCK2,
SCK5 to SCK19
SIN0 to SIN2,
SIN5 to SIN19
34
-
ns
SCK3, SCK4
SIN3, SIN4
300
-
ns
SCK
↓ →
Valid SIN hold time
tSLIXI
SCK0 to SCK19
SIN0 to SIN19
0
-
ns
Serial clock
"H"pulse width
tSHSL
SCK0 to SCK19
-
tCPP+10
-
ns
External shift clock
mode output pin:
CL=50pF
Serial clock
"L" pulse width
tSLSH
2tCPP-10
-
ns
SCK
↑ →
SOT delay time
tSHOVE
SCK0 to SCK2,
SCK5 to SCK19
SOT0 to SOT2,
SOT5 to SOT19
-
33
ns
SCK3, SCK4
SOT3, SOT4
-
300
ns
Valid SIN
→
SCK
↓ setup time
tIVSLE
SCK0 to SCK19
SIN0 to SIN19
10
-
ns
SCK
↓ →
Valid SIN hold time
tSLIXE
20
-
ns
SCK fall time
tF
SCK0 to SCK19
-
5
ns
SCK rise time
tR
SCK0 to SCK19
-
5
ns
Notes:
· AC characteristic in CLK synchronized mode.
· CL is the load capacitance applied to pins during testing.
· The maximum bard rate is limited by internal operation clock used and other parameters. Please use
ch.3 and ch.4 with maximum baud rate 400kbps or less.
See Hardware Manual for details.



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