MB91F528 datasheet(5/241 Pages) SPANSION

5 / 241 page

D a t a S h e e t

MB91F528_DS705-00016-1v0-E, March 28, 2014

CONFIDENTIAL

 FEATURES

 FR81S CPU Core

 32-bit RISC, load/store architecture, 5-stage pipeline

 Maximum operating frequency:

MB91F52xR/MB91F52xU(LQFP): 80 MHz (Source oscillation = 4.0 MHz and 20 multiplied

(PLL clock multiplication system))

MB91F52xR/MB91F52xU(TEQFP): 128 MHz (Source oscillation = 4.0 MHz and 32 multiplied

(PLL clock multiplication system))

MB91F52xM/ MB91F52xY: 128 MHz (Source oscillation = 4.0 MHz and 32 multiplied

(PLL clock multiplication system))

 General-purpose register : 32-bit ×16 sets

 16-bit fixed length instructions (basic instruction), 1 instruction per cycle

 Instructions appropriate to embedded applications

 Memory-to-memory transfer instruction

 Bit processing instruction

 Barrel shift instruction etc.

 High-level language support instructions

 Function entry/exit instructions

 Register content multi-load and store instructions

 Bit search instructions

 Logical 1 detection, 0 detection, and change-point detection

 Branch instructions with delay slot

 Decrease overhead during branch process

 Register interlock function

 Easy assembler writing

 Built-in multiplier and instruction level support

 Signed 32-bit multiplication : 5 cycles

 Signed 16-bit multiplication : 3 cycles

 Interrupt (PC/PS saving)

 6 cycles (16 priority levels)

 The Harvard architecture allows simultaneous execution of program and data access.

 Instruction compatibility with the FR family

 Built-in memory protection function (MPU)

 Eight protection areas can be specified commonly for instructions and the data.

 Control access privilege in both privilege mode and user mode.

 Built-in FPU (floating point arithmetic)

 IEEE754 compliant

 Floating-point register 32-bit × 16 sets

 Peripheral functions

 Clock generation (equipped with SSCG function)

 Main oscillation (4MHz to 16MHz)

 Sub oscillation (32kHz) or no sub oscillation

 PLL multiplication rate : 1 to 20 times for MB91F52xR/MB91F52xU(LQFP)

: 1 to 32 times for MB91F52xR/MB91F52xU(TEQFP)

: 1 to 32 times for MB91F52xM/MB91F52xY

 100 kHz CR oscillator mounted

 Maximum operating frequency:

Peripheral bus clock: 40MHz

External bus clock: 40MHz

 Built-in Program flash capacity

MB91F527 : 1536KB + 64KB

MB91F528 : 2048KB + 64KB

 Built-in Data flash (WorkFlash) 64KB

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