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MB91F528 датащи(PDF) 59 Page - SPANSION |
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MB91F528 датащи(HTML) 59 Page - SPANSION |
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59 / 241 page ![]() D a t a S h e e t 56 MB91F528_DS705-00016-1v0-E, March 28, 2014 CONFIDENTIAL MB91F527U, MB91F528U From Master To Slave From Master To Slave XBS Crossbar Switch FR81s CPU core Instruction Data External Bus I / F Peripheral Bus Bridge CAN prescaler Watchdog timer (SW and HW) Delay interrupt Interrupt controller RTC / WDT1 Calibration I/O port setting Low power consumption setting register 16 32 Wild register Debug Interface Regulator Interrupt request batch read DMA transfer request generate/clear Real time clock Clock supervisor Clock control (Clock setting, Main timer, Sub timer, PLL timer) M P U Clock control (divide control) Bus performance counter BackUp RAM 16KB Timing Protection Unit PPG (48ch) Reload timer (8ch) 8bit DA converter (2ch) External interrupt input (16ch) 32bit Output compare (6ch) Base timer (2ch) U/D counter (2ch) 32bit Free-run timer (3ch) 32bit Input capture (6ch) Multi-function serial interface (12ch) DMAC (16 ch) CAN (6ch) CRC Operation mode register Wave generator (6ch) 12bit AD converter (32ch + 16ch) 16bit Free-run timer (3ch) 16bit Input capture (4ch) Power-on reset CR oscillator Low voltage detection (External power supply low voltage detection) Reset control register NMI Clock monitor Bus Bridge (32bit <-> 16bit) RAM ECC Control(XBS RAM) Clock / Bus Bridge RAM ECC Control (BackUp RAM) Async Bus Bridge (PCLK1 <-> PCLK2) Bus Bridge (32bit <-> 16bit) 16bit Output compare (6ch) Async Bus Bridge (PCLK1 <-> PCLK2) Low voltage detection (Internal power supply low voltage detection) RSTX NMIX MD0,MD1,P006 RX,TX D,A,ASX,CS, RDX,WRX, SYSCLK,RDY FRCK ICU OCU TIOA,TIOB AIN,BIN,ZIN TIN,TOT DAO MONCLK WOT INT TRG,PPG SOUT, SIN, SCK ADTG,AIN ADC enable(ADER) ICU FRCK DTTI,RTO Flex Ray clock control Flex Ray(1ch) RXDA-B,TXDA-B, TXENA-B, STOPWT Flash ・Main Flash 1600KB/2112KB ・Work Flash 64KB RAM 192KB/192KB On chip bus layer 2 On chip bus layer 1 Tuning RAM 0KB/128KB AHB RAM 0KB/128KB JTAG I/F |
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