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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PI7C7300D датащи(PDF) 29 Page - Pericom Semiconductor Corporation |
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PI7C7300D датащи(HTML) 29 Page - Pericom Semiconductor Corporation |
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29 / 107 page  PI7C7300D 3-PORT PCI-TO-PCI BRIDGE Page 29 of 107 Pericom Semiconductor November 2005 - Revision 1.01 Table 4-5 shows the read pre-fetch address boundaries for read transactions during non- flow-through mode. Table 4-4 READ PREFETCH ADDRESS BOUNDARIES Type of Transaction Address Space Cache Line Size (CLS) Prefetch Aligned Address Boundary Configuration Read - * One DWORD (no prefetch) I/O Read - * One DWORD (no prefetch) Memory Read Non-Prefetchable * One DWORD (no prefetch) Memory Read Prefetchable CLS = 0 or 16 16-DWORD aligned address boundary Memory Read Prefetchable CLS = 1, 2, 4, 8, 16 Cache line address boundary Memory Read Line - CLS = 0 or 16 16-DWORD aligned address boundary Memory Read Line - CLS = 1, 2, 4, 8, 16 Cache line boundary Memory Read Multiple - CLS = 0 or 16 32-DWORD aligned address boundary Memory Read Multiple - CLS = 1, 2, 4, 8, 16 2X of cache line boundary - does not matter if it is prefetchable or non-prefetchable * don’t care |
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