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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PI7C7300D датащи(PDF) 21 Page - Pericom Semiconductor Corporation |
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PI7C7300D датащи(HTML) 21 Page - Pericom Semiconductor Corporation |
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21 / 107 page  PI7C7300D 3-PORT PCI-TO-PCI BRIDGE Page 21 of 107 Pericom Semiconductor November 2005 - Revision 1.01 Pin # Name Type Pin # Name Type W15 P_SERR# POD W16 P_AD[14] PB W17 P_AD[12] PB W18 P_AD[9] PB W19 P_AD[6] PB W20 VDD - Y1 AVCC - Y2 S_CFN# PIU Y3 PLL_TM PI Y4 BYPASS - Y5 P_RESET# PI Y6 VSS - Y7 P_AD[31] PB Y8 P_AD[29] PB Y9 P_AD[25] PB Y10 P_IDSEL PI Y11 P_AD[21] PB Y12 P_AD[18] PB Y13 VSS - Y14 P_DEVSEL# PSTS Y15 P_PERR# PSTS Y16 P_AD[13] PB Y17 P_AD[11] PB Y18 P_AD[8] PB Y19 P_AD[5] PB Y20 P_AD[2] PB 4 PCI BUS OPERATION This Chapter offers information about PCI transactions, transaction forwarding across PI7C7300D, and transaction termination. The PI7C7300D has three 128-byte buffers for buffering of upstream and downstream transactions. These hold addresses, data, commands, and byte enables and are used for both read and write transactions. 4.1 TYPES OF TRANSACTIONS This section provides a summary of PCI transactions performed by PI7C7300D. Table 4-1 lists the command code and name of each PCI transaction. The Master and Target columns indicate support for each transaction when PI7C7300D initiates transactions as a master, on the primary (P) and secondary (S1, S2) buses, and when PI7C7300D responds to transactions as a target, on the primary (P) and secondary (S1, S2) buses. Table 4-1 PCI TRANSACTIONS Types of Transactions Initiates as Master Responds as Target Primary Secondary Primary Secondary 0000 Interrupt Acknowledge N N N N 0001 Special Cycle Y Y N N 0010 I/O Read Y Y Y Y 0011 I/O Write Y Y Y Y 0100 Reserved N N N N 0101 Reserved N N N N 0110 Memory Read Y Y Y Y 0111 Memory Write Y Y Y Y 1000 Reserved N N N N 1001 Reserved N N N N 1010 Configuration Read N Y Y N 1011 Configuration Write Y (Type 1 only) Y Y Y (Type 1 only) 1100 Memory Read Multiple Y Y Y Y 1101 Dual Address Cycle Y Y Y Y 1110 Memory Read Line Y Y Y Y 1111 Memory Write and Invalidate Y Y Y Y |
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