PI7C7300D datasheet(7/107 Pages) PERICOM

7 / 107 page

PI7C7300D

3-PORT PCI-TO-PCI BRIDGE

Page 7 of 107

Pericom Semiconductor

November 2005 - Revision 1.01

SUPPORTED COMMANDS ...................................................................................................... 72

13.1

PRIMARY INTERFACE ........................................................................................................... 72

13.2

SECONDARY INTERFACE..................................................................................................... 73

CONFIGURATION REGISTERS ............................................................................................. 73

14.1

CONFIGURATION REGISTER 1 AND 2................................................................................ 75

14.1.1

VENDOR ID REGISTER – OFFSET 00h........................................................................... 75

14.1.2

DEVICE ID REGISTER – OFFSET 00h ............................................................................ 76

14.1.3

COMMAND REGISTER – OFFSET 04h ........................................................................... 76

14.1.4

STATUS REGISTER – OFFSET 04h.................................................................................. 77

14.1.5

REVISION ID REGISTER – OFFSET 08h......................................................................... 78

14.1.6

CLASS CODE REGISTER – OFFEST 08h ........................................................................ 78

14.1.7

CACHE LINE SIZE REGISTER – OFFSET 0Ch ............................................................... 78

14.1.8

PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch................................................ 78

14.1.9

HEADER TYPE REGISTER – OFFSET 0Ch ..................................................................... 79

14.1.10

PRIMARY BUS NUMBER REGISTER – OFFSET 18h ................................................. 79

14.1.11

SECONDARY (S1 or S2) BUS NUMBER REGISTER – OFFSET 18h .......................... 79

14.1.12

SUBORDINATE (S1 or S2) BUS NUMBER REGISTER – OFFSET 18h ...................... 79

14.1.13

SECONDARY LATENCY TIMER REGISTER – OFFSET 18h ...................................... 79

14.1.14

I/O BASE REGISTER – OFFSET 1Ch ........................................................................... 80

14.1.15

I/O LIMIT REGISTER – OFFSET 1Ch .......................................................................... 80

14.1.16

SECONDARY STATUS REGISTER – OFFSET 1Ch...................................................... 80

14.1.17

MEMORY BASE REGISTER – OFFSET 20h................................................................. 81

14.1.18

MEMORY LIMIT REGISTER – OFFSET 20h................................................................ 81

14.1.19

PREFETCHABLE MEMORY BASE REGISTER – OFFSET 24h .................................. 82

14.1.20

PREFETCHABLE MEMORY LIMIT REGISTER – OFFSET 24h ................................. 82

14.1.21

PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER – OFFSET

28h

........................................................................................................................................ 82

14.1.22

PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER – OFFSET

2Ch

........................................................................................................................................ 82

14.1.23

I/O BASE ADDRESS UPPER 16-BITS REGISTER – Offset 30h................................... 83

14.1.24

I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h............................. 83

14.1.25

ECP POINTER REGISTER – OFFSET 34h................................................................... 83

14.1.26

BRIDGE CONTROL REGISTER – OFFSET 3Ch.......................................................... 83

14.1.27

DIAGNOSTIC / CHIP CONTROL REGISTER – OFFSET 40h ..................................... 85

14.1.28

ARBITER CONTROL REGISTER – OFFSET 40h ......................................................... 86

14.1.29

UPSTREAM MEMORY CONTROL REGISTER – OFFSET 48h ................................... 86

14.1.30

HOT SWAP SWITCH TIME SLOT REGISTER – OFFSET 4Ch.................................... 86

14.1.31

UPSTREAM (S1 or S2 to P) MEMORY BASE REGISTER – OFFSET 50h................... 87

14.1.32

UPSTREAM (S1 or S2 to P) MEMORY LIMIT REGISTER – OFFSET 50h.................. 87

14.1.33

UPSTREAM (S1 or S2 to P) MEMORY BASE UPPER 32-BITS REGISTER – OFFSET

54h

........................................................................................................................................ 87

14.1.34

UPSTREAM (S1 or S2 to P) MEMORY LIMIT UPPER 32 BITS REGISTER – OFFSET

58h

........................................................................................................................................ 88

14.1.35

P_SERR# EVENT DISABLE REGISTER – OFFSET 64h .............................................. 88

14.1.36

SECONDARY CLOCK CONTROL REGISTER – OFFSET 68h .................................... 89

14.1.37

PORT OPTION REGISTER – OFFSET 74h .................................................................. 89

14.1.38

MASTER TIMEOUT COUNTER REGISTER – OFFSET 74h ....................................... 91

14.1.39

RETRY COUNTER REGISTER – OFFSET 78h............................................................. 91

14.1.40

SAMPLING TIMER REGISTER – OFFSET 7Ch ........................................................... 91

14.1.41

SECONDARY SUCCESSFUL I/O READ COUNTER REGISTER – OFFSET 80h ....... 91

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