LP3910 datasheet(11/72 Pages) TI1

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LP3910

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SNVS481M – NOVEMBER 2006 – REVISED DECEMBER 2015

7.11 Input Electrical Characteristics: USBSUSP, USBISEL

Unless otherwise noted, VUSB = 5 V, VBATT = 3.6 V, CBATT = 4.7 µF, CCHG_DET = 10 µF. Minimum and maximum limits apply

over the entire junction temperature range for operation, TJ = 0°C to 125°C.

(1) (2) (3) (4) (5)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VIL

Input low level

0.3 × VUSB

VIH

Input high level

0.7 × VUSB

ILEAKAGE

Input leakage

−1

µA

(1)

LDO2EN, BUCK1EN, and USBSUSP have weak internal pulldowns while pins POWERACK, ONOFF do not have weak pulldowns.

(2)

All voltages are with respect to the potential at the GND pin.

(3)

Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power

dissipation exists, special care must be paid to thermal dissipation issues in board design.

(4)

Minimum and maximum limits are specified by design, test, or statistical analysis.

(5)

Low ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.

7.12 Input Electrical Characteristics: POWERACK, ONOFF, LDO2EN, BUCK1EN

Unless otherwise noted, VDD = 5 V, VBATT = 3.6 V, CBATT = 4.7 µF, CCHG_IN = 10 µF. Minimum and maximum limits apply over

the entire junction temperature range for operation, TJ = 0°C to 125°C.

(1) (2) (3) (4) (5)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VIL

Input low level

0.4

VIH

Input high level

1.4

ILEAKAGE

Input leakage

–1

µA

(1)

LDO2EN, BUCK1EN, and USBSUSP have weak internal pulldowns, while pins POWERACK, ONOFF do not have this.

(2)

All voltages are with respect to the potential at the GND pin.

(3)

Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power

dissipation exists, special care must be paid to thermal dissipation issues in board design.

(4)

Minimum and maximum limits are specified by design, test, or statistical analysis.

(5)

Low ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.

7.13 Electrical Characteristics: LDO1 Low Dropout Linear Regulators

Unless otherwise noted, VIN1 = 3.6 V, IMAX = 150 mA, VOUT = default value, CVDD = 10 µF, CLDO1 = 1 µF, ESR = 5 mΩ – 500

Ω, CVREFH = 100 nF. Typical limits apply for TJ = 25°C; minimum and maximum limits apply for TJ = 0°C to 125°C, unless

otherwise specified.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VIN1

Operational voltage

2.5

Output voltage

TJ = 25°C

VOUT Range

1.2

3.3

programming range

1.2 V to 3.3 V in 100-mV steps

1 mA

≤ IOUT ≤ IMAX over full line and

VOUT Accuracy Output voltage accuracy

load regulation.

–3%

VOUT = default value

VIN = (VOUT + 500 mV) to 5.5 V

Line regulation

Load current = IMAX

ΔVOUT

VIN = 3.6 V,

Load regulation

Load current = 1 mA to IMAX

ISC

Short-circuit current limit

VOUT = 0 V

600

750

VIN – VOUT

Dropout voltage

Load current = IMAX

150

Power supply ripple

PSRR

F = 10 kHz, load current = IMAX

rejection

RSHUNT

LDO output impedance

LDO disabled, VOUT = default value

200

Ω

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