VREG

VDD

Above 2.0 V

EN

0.6 V

VREF

VOUT

250 µs

14

TPS53353

SLUSAK2C – AUGUST 2011 – REVISED FEBRUARY 2016

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Functional Block Diagram (continued)

NOTE

The thresholds in this block diagram are typical values. Refer to the Electrical

Characteristics table for threshold limits.

7.3 Feature Description

7.3.1 5-V LDO and VREG Start-Up

TPS53353 provides an internal 5-V LDO function using input from VDD and output to VREG. When the VDD

voltage rises above 2 V, the internal LDO is enabled and outputs voltage to the VREG pin. The VREG voltage

provides the bias voltage for the internal analog circuitry and also provides the supply voltage for the gate drives.

Figure 34. Power Up Sequence

NOTE

The 5-V LDO is not controlled by the EN pin. The LDO starts-up any time VDD rises to

approximately 2 V. (See Figure 34.)

7.3.2 Adaptive On-Time D-CAP™ Control and Frequency Selection

The TPS53353 does not have a dedicated oscillator to determine switching frequency. However, the device

operates with pseudo-constant frequency by feed-forwarding the input and output voltages into the on-time one-

shot timer. The adaptive on-time control adjusts the on-time to be inversely proportional to the input voltage and

This makes the switching frequency fairly constant in steady state conditions over a wide input voltage range.

The switching frequency is selectable from eight preset values by a resistor connected between the RF pin and

GND or between the RF pin and the VREG pin as shown in Table 1. (Maintaining open resistance sets the

switching frequency to 500 kHz.)

Table 1. Resistor and Switching Frequency

CONNECTIONS

SWITCHING

FREQUENCY

(kHz)

VALUE (k

Ω)

CONNECT TO

0

GND

250

187

GND

300