Shutdown

VREG

VDDOK

LL

TPS53353

One-

Shot

Control

Logic

+

ZC

GND

LL

XCON

GND

+

1.2 V/0.95 V

EN

UVP/OVP

Logic

+

THOK

145°C/

135°C

+

4.2 V/

3.95 V

VIN

VBST

Fault

LL

GND

RF

+

+

PWM

+

OV

+20%

UV

+

0.6 V –30%

Delay

SS

0.6 V

VFB

TRIP

Enable

+

+

Delay

0.6 V +10/15%

0.6 V –5/10%

PGOOD

Control Logic

·

On/Off time

·

Minimum On /Off

·

Light load

·

OVP/UVP

·

FCCM/Skip

UDG-11048

10 ?A

VREG

+

SS

FCCM/

Skip

Decode

MODE

VDD

Ramp

Compensation

+

LDO

EN

13

TPS53353

www.ti.com

SLUSAK2C – AUGUST 2011 – REVISED FEBRUARY 2016

Product Folder Links: TPS53353

Submit Documentation Feedback

Copyright © 2011–2016, Texas Instruments Incorporated

7 Detailed Description

7.1 Overview

The TPS53353 is a high-efficiency, single channel, synchronous buck converter suitable for low output voltage

point-of-load applications in computing and similar digital consumer applications. The device features proprietary

D-CAP™ mode control combined with an adaptive on-time architecture. This combination is ideal for building

modern low duty ratio, ultra-fast load step response DC-DC converters. The output voltage ranges from 0.6 V to

5.5 V. The conversion input voltage range is from 1.5 V up to 15 V and the VDD bias voltage is from 4.5 V to 25

V. The D-CAP™ mode uses the equivalent series resistance (ESR) of the output capacitor(s) to sense the device

current . One advantage of this control scheme is that it does not require an external phase compensation

network. This allows a simple design with a low external component count. Eight preset switching frequency

values can be chosen using a resistor connected from the RF pin to ground or VREG. Adaptive on-time control

tracks the preset switching frequency over a wide input and output voltage range while allowing the switching

frequency to increase at the step-up of the load.

The TPS53353 has a MODE pin to select between auto-skip mode and forced continuous conduction mode

(FCCM) for light load conditions. The MODE pin also sets the selectable soft-start time ranging from 0.7 ms to

5.6 ms as shown in Table 3.

7.2 Functional Block Diagram