TPS53353_16 datasheet(23/37 Pages) TI1

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UDG-11050

TRIP

MODE

VDD

VREG VIN

VIN

TPS53353

VFB

PGOOD

VBST

N/C

VOUT

0.1 mF

VREG

CIN

22 mF

GND

0.44 mH

PA 0513 .441

COUT

4 x 100 mF

Ceramic

R1 14.7 kW

10 kW

R10

100 kW

VIN

R11

2 W

CIN

22 mF

CIN

22 mF

CIN

22 mF

8 V

14 V

200 kW

110 kW

4.7 mF

1 mF

VVDD

4.5 V to 25 V

3.01 kW

0.1 mF

1 nF

PGOOD

TPS53353

www.ti.com

SLUSAK2C – AUGUST 2011 – REVISED FEBRUARY 2016

Product Folder Links: TPS53353

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8.2.2 Typical Application Circuit Diagram With Ceramic Output Capacitors

Figure 41. Typical Application Circuit Diagram With Ceramic Output Capacitors

8.2.2.1 Design Requirements

Table 5. Design Parameters

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT CHARACTERISTICS

VIN

Voltage range

IMAX

Maximum Input current

VIN = 8 V, IOUT = 20 A

4.1

No load input current

VIN = 14 V, IOUT = 0 A with auto-skip mode

OUTPUT CHARACTERISTICS

VOUT

Output voltage

1.5

Output voltage regulation

Line regulation, 8 V

≤ VIN ≤ 15 V

0.1%

Load regulation, VIN = 12 V, 0 A ≤ IOUT ≤ 20

A with FCCM

0.2%

VRIPPLE

Output voltage ripple

VIN = 12 V, IOUT = 20 A with FCCM

mVPP

ILOAD

Output load current

IOCP

Output overcurrent

threshold

tSS

Soft-start time

1.4

SYSTEMS CHARACTERISTICS

fSW

Switching frequency

500

kHz

Peak efficiency

VIN = 12 V, VOUT = 1.1 V, IOUT = 10 A

91.87%

Full load efficiency

VIN = 12 V, VOUT = 1.1 V, IOUT = 20 A

91.38%

Operating temperature

°C

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