Silicon Image, Inc.

Subject to Change without Notice

Si

Datasheet

March 2001

General Description

Features

The Si

I 161A receiver uses PanelLink Digital technology to support high

resolution displays up to UXGA. The Si

I 161A receiver supports up to true

color panels (24 bit/pixel, 16.7M colors) in 1 or 2 pixels/clock mode.

In

addition, the receiver data output is time staggered to reduce ground bounce

that affects EMI. Since all PanelLink products are designed on scaleable

CMOS architecture to support future performance requirements while

maintaining the same logical interface, system designers can be assured that

the interface will be fixed through a number of technology and performance

generations.

PanelLink Digital technology simplifies PC and display interface design

by resolving many of the system level issues associated with high-speed

mixed signal design, providing the system designer with a digital interface

solution that is quicker to market and lower in cost.

•

Low Power: 3.3V core operation

•

Time staggered data output for reduced ground

bounce

•

Sync Detect: for Plug & Display “Hot Plugging”

•

Cable Distance Support: over 5m with twisted-pair,

fiber-optics ready

•

Compliant with DVI 1.0 (DVI is backwards

compatible with VESA

§

Supports Dual-Link operation up to 330 Mega-

pixels/second

Si

S_D

1

SiI 161A

100-Pin TQFP

(Top View)

PD

2

ST

3

PIXS/M_S

4

GND

5

VCC

6

STAG_OUT/SYNC

7

SCDT

8

PDO

9

QE0

10

QE1

11

QE2

12

QE3

13

QE4

14

QE5

15

QE6

16

QE7

17

OVCC

18

OGND

19

QE8

20

QE9

21

QE10

22

QE11

23

QE12

24

QE13

25

75

QO21

74

QO20

73

QO19

72

QO18

71

QO17

70

QO16

69

GND

68

VCC

67

QO15

66

QO14

65

QO13

64

QO12

63

QO11

62

QO10

61

QO9

60

QO8

59

OGND

58

OVCC

57

QO7

56

QO6

55

QO5

54

QO4

53

QO3

52

QO2

51

QO22

DIFFERENTIALSIGNAL

EVEN 8-bits RED

PLL

GPO

CONTROLS