Silicon Image, Inc.

Silicon Image, Inc.

5

Subject to Change without Notice

AC Specifications

Under normal operating conditions unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Intra-Pair (+ to -) Differential Input Skew

1

165MHz

245

ps

Channel to Channel Differential Input Skew

1

165MHz

4

ns

Worst Case Differential Input Clock Jitter

65 MHz

465

ps

tolerance

2,3

112 MHz

270

ps

165 MHz

182

ps

Low-to-High Transition Time: Data and Controls

(70 C, 82.5 MHz, 2-pixel/clock, PIXS=1)

ST = 1

2.6

ns

ST = 0

2.7

ns

Low-to-High Transition Time: Data and Controls

(70 C, 165 MHz, 1-pixel/clock, PIXS=0)

ST = 1

2.4

ns

ST = 0

3.0

ns

Low-to-High Transition Time: ODCK

(70 C, 82.5 MHz, 2-pixel/clock, PIXS=1)

ST = 1

1.3

ns

ST = 0

1.7

ns

Low-to-High Transition Time: ODCK

(70 C, 165 MHz, 1-pixel/clock, PIXS=0)

ST = 1

1.4

ns

ST = 0

1.7

ns

High-to-Low Transition Time: Data and Controls

(70 C, 82.5 MHz, 2-pixel/clock, PIXS=1)

ST = 1

2.8

ns

ST = 0

3.4

ns

High-to-Low Transition Time: Data and Controls

(70 C, 165 MHz, 1-pixel/clock, PIXS=0)

ST = 1

2.3

ns

ST = 0

3.3

ns

High-to-Low Transition Time: ODCK

(70 C, 82.5 MHz, 2-pixel/clock, PIXS=1)

ST = 1

1.1

ns

ST = 0

1.5

ns

High-to-Low Transition Time: ODCK

(70 C, 165 MHz, 1-pixel/clock, PIXS=0)

ST = 1

1.2

ns

ST = 0

1.5

ns

Data, DE, VSYNC, HSYNC, and CTL[3:1] Setup

Time to ODCK falling edge (OCK_INV = 0) or to

ODCK rising edge (OCK_INV = 1) at 165 MHz

ST = 1

0.7

*0.7

ns

*OCK_INV = 1

ST = 0

0.7

*0.4

ns

Data, DE, VSYNC, HSYNC, and CTL[3:1] Hold Time

from ODCK falling edge, (OCK_INV = 0) or from

ODCK rising edge (OCK_INV = 1) at 165 MHz,

ST = 1

3.8

*3.8

ns

*OCK_INV = 0

ST = 0

4.2

*3.8

ns

Notes:

1

Guaranteed by design.

2

Jitter defined as per DVI 1.0 Specification, Section 4.6 Jitter Specification.

3

Jitter measured with Clock Recovery Unit as per DVI 1.0 Specification, Section 4.7 Electrical Measurement Procedures .

4

Output clock duty cycle is independent of the differential input clock duty cycle and the IDCK duty cycle.

5

Measured when transmitter was powered down (see Si

I /AN-0005 “PanelLink Basic Design/Application Guide,” Section 2.4).