9

36-00-01-006

Ver.

1.9.4

Aeroflex Microelectronics Solutions - HiRel

Notes:

* All chip selects active when L, at least one chip select inactive when H

1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW

2. Write is defined by WE and FLSH_PIPE.

3. When a Write cycle is detected, all I/Os are tri-stated.

4. The DQ pins are controlled by the current cycle and the OE signal.

5. CEN = H inserts wait states.

6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.

Table 6. 288-Lead Flow-thru Signal Locations

Operation

Address

Used

CSx*

ZZ

SHUT

DOWN

ADV_LD

WE

FLSH_

PIPE

OE

CEN

CLK

DQs

Standby Mode

None

H

L

L

L

X

X

X

L

L-H

3-State

Continue Deselect

None

X

L

L

H

X

X

X

L

L-H

3-State

Read Cycle (Start Burst)

External

L

L

L

L

H

X

L

L

L-H

Data Out

Read Cycle (Cont. Burst)

Next

X

L

L

H

X

X

L

L

L-H

Data Out

NOP/Dummy Read

(Start)

External

L

L

L

L

H

X

H

L

L-H

3-State

NOP/Dummy Read

(Cont.)

Next

X

L

L

H

X

X

H

L

L-H

3-State

Write Cycle (Start Burst)

External

L

L

L

L

L

L

X

L

L-H

Data In

Write Cycle (Cont. Burst)

Next

X

L

L

H

X

L

X

L

L-H

Data In

Dummy Write (Start)

None

L

L

L

L

L

H

X

L

L-H

3-State

Dummy Write (Cont.

Burst)

Next

X

L

L

H

X

H

X

L

L-H

3-State

Clock Inhibit (Stall)

N/A

X

L

L

X

X

X

X

H

L-H

N/A

Sleep Mode

N/A

H

H

L

X

X

X

X

X

X

3-State

Shutdown Mode

None

X

X

H

X

X

X

X

X

X

3-State