UT8SF2M32MSFC datasheet(8/27 Pages) AEROFLEX

8 / 27 page

36-00-01-006

Ver.

1.9.4

Aeroflex Microelectronics Solutions - HiRel

Power Up/ Down Requirements

The SSRAM requires that VDD < VDDQ at all times. The

SSRAM does require the user to provide an external reset after

initial power application, exiting shutdown mode, or any

power interruption to the device input voltage outside the

specified limit. Performing a reset requires the assertion of the

/RESET device input lead (LOW) for a minimum of 1us

(tRLRH). After the /RESET input is returned HIGH, the device

requires 50us (tSHTDWNREC) to complete the reset operation.

Once the reset operation is complete, the device requires an

additional 20us (tCR) to synchronize the clock input providing

a stable input clock is present. The device READY output lead

asserts HIGH once tCR is satisfied at the next rising clock. The

READY out lead HIGH indicates the device is available for

normal operations. For power down it is required that VDD and

VDDQ be powered down to <0.5V for a minimum of 100ms.

Clock Conditioning Requirements

The CLK signal input requirements are given in the Clock

section of the AC Characterizations. AC Characterization

performances listed herein are based on providing a clock

input signal meeting these requirements.

Changing Clock Frequencies

The CLK input frequency should be established at power on,

and may only be changed while in SLEEP mode (reference

Table 5).

External Connections

A precision 25kohm < +0.2% low TCR < 25ppm/oC resistor is

required to be connected between device pin EXTRES (R15)

and VSS.

In order to ensure proper operation in conjunction with JTAG

boundary (reference applications note MEM-AN-005) and

EDAC bypass capabilities, Aeroflex requires that specific

package pins be biased through soft connections to either VDD,

VDDQ or VSS. Table 4 below is a list of these required external

biases.

Notes:

1. NUIL = Not Used Input Low

2. NUIH = Not Used Input High

3. Aeroflex recommends connecting all DQ[51:0] to either VDDQ or VSS

through >10kΩ resistors.

Table 4. External Bias Conditions

Signal Name

Package Pin

Bias Condition

NUIL1

P13, R7, R8, R12,

R13, R14, R16

>10kΩ to VSSQ

NUIH2

P16

>10kΩ to VDDQ

TDO

>10kΩ to VDDQ

TCK

>10kΩ to VSSQ

DQ[51:0]4

ref Table 6

>10kΩ to VDDQ

orVSSQ

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