UT8SF2M32MSFC datasheet(7/27 Pages) AEROFLEX

7 / 27 page

36-00-01-006

Ver.

1.9.4

Aeroflex Microelectronics Solutions - HiRel

To avoid bus contention data should not be driven to DQs

when outputs are active. The Output Enable (OE) may be

disabled HIGH before applying data to the DQ lines. This will

tri-state the DQ output drivers. As an additional feature DQ

lines are automatically tri-stated during the data portion of a

Write cycle, regardless of the state of OE.

Burst Write Accesses

The UT8SF2M32 has an internal burst counter allowing up to

four writes to be performed from a single address input. A new

address can only be loaded when ADV_LD is driven LOW.

New addresses are loaded into the SSRAM, as described the

Single Write Access section. When ADV_LD is driven HIGH

where CEN is LOW on the subsequent clock rise, the Chip

Enables (CS0, CS1, CS2) and WE inputs are ignored and the

burst counter is incremented. The FLSH_PIPE input must be

LOW in each cycle of the burst write in order to write the

correct data.

READY Status

The UT8SF2M32 device operates as a Synchronous SRAM

device. Data integrity housekeeping activities are performed in

the background during normal user activity. These

housekeeping activities are performed on a regular basis.

However, when a housekeeping activity sequence cannot be

completed due to user conflict for memory space, the READY

pin asserts signifying to the user that an idle cycle is required.

Please reference applications note AN-MEM-004 for more

information.

Data Scrubbing

The UT8SF2M32 device employs internal autonomous data

scrubbing. The scrub circuit cycles through all address spaces

typically once every 0.5 seconds. Scrub cycles occur anytime

power is applied provided SCRUBEN is HIGH. When the

EDAC circuit is disabled via EDACEN input LOW,

DQ[51:32] pins are available for read and write accesses.

However if the SCRUBEN is not also disabled, data written to

DQ[51:32] could be changed by the internal data scrubbing

activity.

FLSH_PIPE

The write operation consists of two register stages. Writing

data to the core memory requires three subsequent write

operations. Dummy write operations can be performed using

the FLSH_PIPE inputs. Because data coherency is always

maintained and the SEU error rate includes the pipeline

registers, flushing the pipeline is not necessary.

Sleep Mode

The ZZ input lead is a synchronous input. Asserting the ZZ pin

HIGH places the SSRAM into a power conservative "sleep"

mode. To assure the completion of previous commands

through the pipeline prior to entering sleep mode, a minimum

of two full clock cycles (tZZS) are required between the last

operation command and asserting the ZZ input. While in sleep

mode, data integrity is guaranteed. Changing the input clock

frequency or halting the input clock may be executed during

sleep mode. The device must be deselected prior to entering

sleep mode and remain deselected for the duration of tZZREC

after the ZZ input returns LOW.

Shutdown Mode

The SHUTDOWN input pin is an asynchronous input.

Asserting SHUTDOWN places the device in a power saving

shutdown mode. The system clock can be stopped. Memory

contents are not maintained in shutdown mode. The SSRAM

requires a reset upon exiting shutdown mode.

Table 2. Linear Burst Address Table

(MODE= VSS)

Starting

Address

Second

Address

Third

Address

Fourth

Address

A1, A0

Table 3. Interleaved Burst Address Table

(MODE=VDDQ)

Starting

Address

Second

Address

Third

Address

Fourth

Address

A1, A0

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