VX6854LC datasheet(38/114 Pages) STMICROELECTRONICS

номер детали	VX6854LC

подробное описание детали	QXGA EDOF camera module

PDF	114 Pages

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производитель	STMICROELECTRONICS [STMicroelectronics]

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VX6854LC

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DocID027110 Rev 2

4.11

Fifo water mark registers [0x0700 to 0x0701]

4.12

DPHY registers [0x0810 to 0x0811]

4.13

Binning registers [0x0900 to 0x0902]

Table 22. Fifo water mark registers [0x0700 to 0x0701]

Index

Byte

Data type Default Type

Comment

0x0700

fifo_water_mark_pixels

16UI

00.28

The level at which data starts to be

transmitted out of the FIFO (default =

40)

0x0701

Table 23. DPHY registers [0x0810 to 0x0811]

Index

Byte

Data type Default Type

Comment

0x0820

dphy_channel_mbps_for_ui

32UI

00.00

CSI-2 DPHY channel in Mbps (16.16

fixed point)

This is used by the DPHY to calculate

UI(Unit Interval) value.

It does not control the sensor clock

set-up, but should normally

correspond to those settings.

0: Sensor automatically calculates UI

from the op_sys_clk_freq_mhz value.

80-800: Sensor calculates UI from this

value.

0x0821

3rd

0x0822

2nd

0x0823

Table 24. Binning registers [0x0900 to 0x0902]

Index

Byte

Data type Default Type

Comment

0x0900

binning_mode

8UI

Binning Mode

0 - Disabled

1 - Enabled

0x0901

binning_type

8UI

High-nibble - column binning factor

Low-nibble - row binning factor

0x0902

binning_weighting

8UI

bit0: Averaged (1-enable)

bit2: Bayer corrected (1-enable)

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