VX6854LC datasheet(52/114 Pages) STMICROELECTRONICS

номер детали	VX6854LC

подробное описание детали	QXGA EDOF camera module

PDF	114 Pages

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Video data interface

VX6854LC

52/114

DocID027110 Rev 2

Video data interface

The video stream which is output from the VX6854LC using the compact camera port (CCP)

or camera serial interface (CSI) contains both video data and other auxiliary information.

This chapter describes the frame formats.

The VX6854LC is SMIA version 1.0 and MIPI CSI-2 version 1.00 and D-PHY 0.90

compliant.

The selection of the video data format is controlled using the following register:

CSI_SIGNALLING_MODE (0x0111)

0 - CCP2 Data/Clock

1 - CCP2 Data/strobe

2 - CSI-2 (default)

Changing the video data format must be performed when the sensor is in software standby.

•

The VX6854LC has one CSI-2 data lane capable of transmitting at 800 Mbps.

•

The CSI-2 data lane transmitter supports:

–

unidirectional master

–HS-TX

–

LP-TX (ULPS)

–

CIL-MUYN function

•

The CSI-2 clock lane transmitter supports:

–

unidirectional master

–HS-TX

–

LP-TX (ULPS)

–

CIL-MCNN function

5.1

Frame format

The frame format for the VX6854LC is described by the frame format description registers,

see Table 13 on page 31. For CCP this results in a frame as shown in Figure 12 and for CSI

it results in a frame as shown in Figure 13.

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